symbiflow-arch-defs
symbiflow-arch-defs

tieoff

Component Diagram

(* whitebox *) module TIEOFF( HARD0, HARD1 ); output wire HARD0; output wire HARD1; assign HARD0 = 0; assign HARD1 = 1; endmodule

Internal Diagram

/home/docs/checkouts/readthedocs.org/user_builds/rw1nkler-symbiflow-arch-defs/checkouts/latest/xc/common/primitives/tieoff/tieoff.sim.v

Verilog File

(* whitebox *)
module TIEOFF(
	HARD0, HARD1
);
	output wire HARD0;
	output wire HARD1;

  assign HARD0 = 0;
  assign HARD1 = 1;
endmodule