symbiflow-arch-defs
symbiflow-arch-defs

ilogice3

Physical Block XML

<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="ILOGICE3" num_pb="1">
  <input name="BITSLIP" num_pins="1"/>
  <input name="CE1" num_pins="1"/>
  <input name="CE2" num_pins="1"/>
  <clock name="CLK" num_pins="1"/>
  <clock name="CLKB" num_pins="1"/>
  <clock name="CLKDIV" num_pins="1"/>
  <clock name="CLKDIVP" num_pins="1"/>
  <input name="D" num_pins="1"/>
  <input name="DDLY" num_pins="1"/>
  <input name="DYNCLKDIVPSEL" num_pins="1"/>
  <input name="DYNCLKDIVSEL" num_pins="1"/>
  <input name="DYNCLKSEL" num_pins="1"/>
  <clock name="OCLK" num_pins="1"/>
  <clock name="OCLKB" num_pins="1"/>
  <input name="OFB" num_pins="1"/>
  <input name="SHIFTIN1" num_pins="1"/>
  <input name="SHIFTIN2" num_pins="1"/>
  <input name="SR" num_pins="1"/>
  <input name="TFB" num_pins="1"/>
  <output name="O" num_pins="1"/>
  <output name="Q1" num_pins="1"/>
  <output name="Q2" num_pins="1"/>
  <output name="Q3" num_pins="1"/>
  <output name="Q4" num_pins="1"/>
  <output name="Q5" num_pins="1"/>
  <output name="Q6" num_pins="1"/>
  <output name="Q7" num_pins="1"/>
  <output name="Q8" num_pins="1"/>
  <output name="SHIFTOUT1" num_pins="1"/>
  <output name="SHIFTOUT2" num_pins="1"/>
  <mode name="PASS_THROUGH">
    <interconnect>
      <direct name="D_O" input="ILOGICE3.D" output="ILOGICE3.O">
        <metadata>
          <meta name="fasm_mux">
            ILOGICE3.D : ZINV_D
          </meta>
        </metadata>
      </direct>
    </interconnect>
  </mode>
  <mode name="ISERDES_NO_IDELAY">
    <pb_type name="ISERDESE2_NO_IDELAY" blif_model=".subckt ISERDESE2_NO_IDELAY_VPR" num_pb="1">
      <clock name="CLK" num_pins="1"/>
      <clock name="CLKB" num_pins="1"/>
      <clock name="CLKDIV" num_pins="1"/>
      <input name="BITSLIP" num_pins="1"/>
      <input name="CE1" num_pins="1"/>
      <input name="CE2" num_pins="1"/>
      <input name="D" num_pins="1"/>
      <input name="DYNCLKDIVPSEL" num_pins="1"/>
      <input name="DYNCLKDIVSEL" num_pins="1"/>
      <input name="DYNCLKSEL" num_pins="1"/>
      <clock name="OCLK" num_pins="1"/>
      <clock name="OCLKB" num_pins="1"/>
      <input name="OFB" num_pins="1"/>
      <input name="SHIFTIN1" num_pins="1"/>
      <input name="SHIFTIN2" num_pins="1"/>
      <input name="RST" num_pins="1"/>
      <input name="TFB" num_pins="1"/>
      <output name="O" num_pins="1"/>
      <output name="Q1" num_pins="1"/>
      <output name="Q2" num_pins="1"/>
      <output name="Q3" num_pins="1"/>
      <output name="Q4" num_pins="1"/>
      <output name="Q5" num_pins="1"/>
      <output name="Q6" num_pins="1"/>
      <output name="Q7" num_pins="1"/>
      <output name="Q8" num_pins="1"/>
      <output name="SHIFTOUT1" num_pins="1"/>
      <output name="SHIFTOUT2" num_pins="1"/>

      <T_clock_to_Q max="{iopath_CLKDIV_Q1}" clock="CLKDIV" port="Q1"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q2}" clock="CLKDIV" port="Q2"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q3}" clock="CLKDIV" port="Q3"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q4}" clock="CLKDIV" port="Q4"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q5}" clock="CLKDIV" port="Q5"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q6}" clock="CLKDIV" port="Q6"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q7}" clock="CLKDIV" port="Q7"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q8}" clock="CLKDIV" port="Q8"/>

      <!-- Unclear what this is for, but VPR wants it... -->
      <T_clock_to_Q max="0.0" port="D" clock="CLK"/>
      <T_clock_to_Q max="0.0" port="OFB" clock="CLK"/>

      <delay_constant max="{iopath_OFB_O}" in_port="OFB" out_port="O"/>
      <delay_constant max="{iopath_D_O}" in_port="D" out_port="O"/>
      <delay_constant max="{iopath_TFB_O}" in_port="TFB" out_port="O"/>

      <T_setup value="{setup_CLK_OFB}" port="OFB" clock="CLK"/>
      <T_hold value="{hold_CLK_OFB}" port="OFB" clock="CLK"/>

      <T_setup value="{setup_CLK_D}" port="D" clock="CLK"/>
      <T_hold value="{hold_CLK_D}" port="D" clock="CLK"/>

      <T_setup value="{setup_CLKDIV_BITSLIP}" port="BITSLIP" clock="CLKDIV"/>
      <T_hold value="{hold_CLKDIV_BITSLIP}" port="BITSLIP" clock="CLKDIV"/>

      <T_setup value="{setup_CLKDIV_CE1}" port="CE1" clock="CLKDIV"/>
      <T_hold value="{hold_CLKDIV_CE1}" port="CE1" clock="CLKDIV"/>

      <T_setup value="{setup_CLKDIV_CE2}" port="CE2" clock="CLKDIV"/>
      <T_hold value="{hold_CLKDIV_CE2}" port="CE2" clock="CLKDIV"/>

      <T_setup value="{setup_CLKDIV_RST}" port="RST" clock="CLKDIV"/>
      <T_hold value="{hold_CLKDIV_RST}" port="RST" clock="CLKDIV"/>

      <metadata>
        <!-- TODO: Some features are named after the IFF site, but do enable functionalities for the ISERDES -->
        <meta name="fasm_features">
          ISERDES.IN_USE
          IDDR_OR_ISERDES.IN_USE
          IFF.DDR_CLK_EDGE.OPPOSITE_EDGE
          IFF.SRTYPE.SYNC
          ISERDES.MODE.MASTER
        </meta>
        <meta name="fasm_params">

          ISERDES.MEMORY_DDR3.DDR.W4 = MEMORY_DDR3_4
          ISERDES.MEMORY.DDR.W4 = MEMORY_DDR_4
          ISERDES.MEMORY_QDR.DDR.W4 = MEMORY_QDR_4

          ISERDES.NETWORKING.SDR.W2 = NETWORKING_SDR_2
          ISERDES.NETWORKING.SDR.W3 = NETWORKING_SDR_3
          ISERDES.NETWORKING.SDR.W4 = NETWORKING_SDR_4
          ISERDES.NETWORKING.SDR.W5 = NETWORKING_SDR_5
          ISERDES.NETWORKING.SDR.W6 = NETWORKING_SDR_6
          ISERDES.NETWORKING.SDR.W7 = NETWORKING_SDR_7
          ISERDES.NETWORKING.SDR.W8 = NETWORKING_SDR_8

          ISERDES.NETWORKING.DDR.W4 = NETWORKING_DDR_4
          ISERDES.NETWORKING.DDR.W6 = NETWORKING_DDR_6
          ISERDES.NETWORKING.DDR.W8 = NETWORKING_DDR_8
          ISERDES.NETWORKING.DDR.W10 = NETWORKING_DDR_10
          ISERDES.NETWORKING.DDR.W14 = NETWORKING_DDR_14

          ISERDES.OVERSAMPLE.DDR.W4 = OVERSAMPLE_DDR_4

          ISERDES.NUM_CE.N1 = NUM_CE_N1
          ISERDES.NUM_CE.N2 = NUM_CE_N2

          IFFDELMUXE3.P0 = IOBDELAY_IFD
          IDELMUXE3.P0 = IOBDELAY_IBUF

          IFF.ZINIT_Q1 = ZINIT_Q1
          IFF.ZINIT_Q2 = ZINIT_Q2
          IFF.ZINIT_Q3 = ZINIT_Q3
          IFF.ZINIT_Q4 = ZINIT_Q4

          IFF.ZSRVAL_Q1 = ZSRVAL_Q1
          IFF.ZSRVAL_Q2 = ZSRVAL_Q2
          IFF.ZSRVAL_Q3 = ZSRVAL_Q3
          IFF.ZSRVAL_Q4 = ZSRVAL_Q4

          IFF.ZINV_C = ZINV_C

          ZINV_D = ZINV_D
        </meta>
      </metadata>
    </pb_type>
    <interconnect>
      <direct name="BITSLIP" input="ILOGICE3.BITSLIP" output="ISERDESE2_NO_IDELAY.BITSLIP"/>
      <direct name="CE1" input="ILOGICE3.CE1" output="ISERDESE2_NO_IDELAY.CE1"/>
      <direct name="CE2" input="ILOGICE3.CE2" output="ISERDESE2_NO_IDELAY.CE2"/>
      <direct name="CLK" input="ILOGICE3.CLK" output="ISERDESE2_NO_IDELAY.CLK"/>
      <direct name="CLKB" input="ILOGICE3.CLKB" output="ISERDESE2_NO_IDELAY.CLKB"/>
      <direct name="CLKDIV" input="ILOGICE3.CLKDIV" output="ISERDESE2_NO_IDELAY.CLKDIV"/>
      <direct name="D" input="ILOGICE3.D" output="ISERDESE2_NO_IDELAY.D"/>
      <direct name="DYNCLKDIVPSEL" input="ILOGICE3.DYNCLKDIVPSEL" output="ISERDESE2_NO_IDELAY.DYNCLKDIVPSEL"/>
      <direct name="DYNCLKDIVSEL" input="ILOGICE3.DYNCLKDIVSEL" output="ISERDESE2_NO_IDELAY.DYNCLKDIVSEL"/>
      <direct name="DYNCLKSEL" input="ILOGICE3.DYNCLKSEL" output="ISERDESE2_NO_IDELAY.DYNCLKSEL"/>
      <direct name="OCLK" input="ILOGICE3.OCLK" output="ISERDESE2_NO_IDELAY.OCLK"/>
      <direct name="OCLKB" input="ILOGICE3.OCLKB" output="ISERDESE2_NO_IDELAY.OCLKB"/>
      <direct name="OFB" input="ILOGICE3.OFB" output="ISERDESE2_NO_IDELAY.OFB"/>
      <direct name="SHIFTIN1" input="ILOGICE3.SHIFTIN1" output="ISERDESE2_NO_IDELAY.SHIFTIN1"/>
      <direct name="SHIFTIN2" input="ILOGICE3.SHIFTIN2" output="ISERDESE2_NO_IDELAY.SHIFTIN2"/>
      <direct name="SR" input="ILOGICE3.SR" output="ISERDESE2_NO_IDELAY.RST"/>
      <direct name="TFB" input="ILOGICE3.TFB" output="ISERDESE2_NO_IDELAY.TFB"/>
      <direct name="O" input="ISERDESE2_NO_IDELAY.O" output="ILOGICE3.O"/>
      <direct name="Q1" input="ISERDESE2_NO_IDELAY.Q1" output="ILOGICE3.Q1"/>
      <direct name="Q2" input="ISERDESE2_NO_IDELAY.Q2" output="ILOGICE3.Q2"/>
      <direct name="Q3" input="ISERDESE2_NO_IDELAY.Q3" output="ILOGICE3.Q3"/>
      <direct name="Q4" input="ISERDESE2_NO_IDELAY.Q4" output="ILOGICE3.Q4"/>
      <direct name="Q5" input="ISERDESE2_NO_IDELAY.Q5" output="ILOGICE3.Q5"/>
      <direct name="Q6" input="ISERDESE2_NO_IDELAY.Q6" output="ILOGICE3.Q6"/>
      <direct name="Q7" input="ISERDESE2_NO_IDELAY.Q7" output="ILOGICE3.Q7"/>
      <direct name="Q8" input="ISERDESE2_NO_IDELAY.Q8" output="ILOGICE3.Q8"/>
      <direct name="SHIFTOUT1" input="ISERDESE2_NO_IDELAY.SHIFTOUT1" output="ILOGICE3.SHIFTOUT1"/>
      <direct name="SHIFTOUT2" input="ISERDESE2_NO_IDELAY.SHIFTOUT2" output="ILOGICE3.SHIFTOUT2"/>
    </interconnect>
  </mode>
  <mode name="ISERDES_IDELAY">
    <pb_type name="ISERDESE2_IDELAY" blif_model=".subckt ISERDESE2_IDELAY_VPR" num_pb="1">
      <clock name="CLK" num_pins="1"/>
      <clock name="CLKB" num_pins="1"/>
      <clock name="CLKDIV" num_pins="1"/>
      <input name="BITSLIP" num_pins="1"/>
      <input name="CE1" num_pins="1"/>
      <input name="CE2" num_pins="1"/>
      <input name="DDLY" num_pins="1"/>
      <input name="DYNCLKDIVPSEL" num_pins="1"/>
      <input name="DYNCLKDIVSEL" num_pins="1"/>
      <input name="DYNCLKSEL" num_pins="1"/>
      <clock name="OCLK" num_pins="1"/>
      <clock name="OCLKB" num_pins="1"/>
      <input name="OFB" num_pins="1"/>
      <input name="SHIFTIN1" num_pins="1"/>
      <input name="SHIFTIN2" num_pins="1"/>
      <input name="RST" num_pins="1"/>
      <input name="TFB" num_pins="1"/>
      <output name="O" num_pins="1"/>
      <output name="Q1" num_pins="1"/>
      <output name="Q2" num_pins="1"/>
      <output name="Q3" num_pins="1"/>
      <output name="Q4" num_pins="1"/>
      <output name="Q5" num_pins="1"/>
      <output name="Q6" num_pins="1"/>
      <output name="Q7" num_pins="1"/>
      <output name="Q8" num_pins="1"/>
      <output name="SHIFTOUT1" num_pins="1"/>
      <output name="SHIFTOUT2" num_pins="1"/>

      <T_clock_to_Q max="{iopath_CLKDIV_Q1}" clock="CLKDIV" port="Q1"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q2}" clock="CLKDIV" port="Q2"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q3}" clock="CLKDIV" port="Q3"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q4}" clock="CLKDIV" port="Q4"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q5}" clock="CLKDIV" port="Q5"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q6}" clock="CLKDIV" port="Q6"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q7}" clock="CLKDIV" port="Q7"/>
      <T_clock_to_Q max="{iopath_CLKDIV_Q8}" clock="CLKDIV" port="Q8"/>

      <!-- Unclear what this is for, but VPR wants it... -->
      <T_clock_to_Q max="0.0" port="DDLY" clock="CLK"/>
      <T_clock_to_Q max="0.0" port="OFB" clock="CLK"/>

      <delay_constant max="{iopath_OFB_O}" in_port="OFB" out_port="O"/>
      <delay_constant max="{iopath_DDLY_O}" in_port="DDLY" out_port="O"/>
      <delay_constant max="{iopath_TFB_O}" in_port="TFB" out_port="O"/>

      <T_setup value="{setup_CLK_OFB}" port="OFB" clock="CLK"/>
      <T_hold value="{hold_CLK_OFB}" port="OFB" clock="CLK"/>

      <T_setup value="{setup_CLK_DDLY}" port="DDLY" clock="CLK"/>
      <T_hold value="{hold_CLK_DDLY}" port="DDLY" clock="CLK"/>

      <T_setup value="{setup_CLKDIV_BITSLIP}" port="BITSLIP" clock="CLKDIV"/>
      <T_hold value="{hold_CLKDIV_BITSLIP}" port="BITSLIP" clock="CLKDIV"/>

      <T_setup value="{setup_CLKDIV_CE1}" port="CE1" clock="CLKDIV"/>
      <T_hold value="{hold_CLKDIV_CE1}" port="CE1" clock="CLKDIV"/>

      <T_setup value="{setup_CLKDIV_CE2}" port="CE2" clock="CLKDIV"/>
      <T_hold value="{hold_CLKDIV_CE2}" port="CE2" clock="CLKDIV"/>

      <T_setup value="{setup_CLKDIV_RST}" port="RST" clock="CLKDIV"/>
      <T_hold value="{hold_CLKDIV_RST}" port="RST" clock="CLKDIV"/>

      <metadata>
        <meta name="fasm_features">
          ISERDES.IN_USE
          IDDR_OR_ISERDES.IN_USE
          IFF.DDR_CLK_EDGE.OPPOSITE_EDGE
          IFF.SRTYPE.SYNC
          ISERDES.MODE.MASTER
        </meta>
        <meta name="fasm_params">
          ISERDES.MEMORY_DDR3.DDR.W4 = MEMORY_DDR3_4
          ISERDES.MEMORY.DDR.W4 = MEMORY_DDR_4
          ISERDES.MEMORY_QDR.DDR.W4 = MEMORY_QDR_4

          ISERDES.NETWORKING.SDR.W2 = NETWORKING_SDR_2
          ISERDES.NETWORKING.SDR.W3 = NETWORKING_SDR_3
          ISERDES.NETWORKING.SDR.W4 = NETWORKING_SDR_4
          ISERDES.NETWORKING.SDR.W5 = NETWORKING_SDR_5
          ISERDES.NETWORKING.SDR.W6 = NETWORKING_SDR_6
          ISERDES.NETWORKING.SDR.W7 = NETWORKING_SDR_7
          ISERDES.NETWORKING.SDR.W8 = NETWORKING_SDR_8

          ISERDES.NETWORKING.DDR.W4 = NETWORKING_DDR_4
          ISERDES.NETWORKING.DDR.W6 = NETWORKING_DDR_6
          ISERDES.NETWORKING.DDR.W8 = NETWORKING_DDR_8
          ISERDES.NETWORKING.DDR.W10 = NETWORKING_DDR_10
          ISERDES.NETWORKING.DDR.W14 = NETWORKING_DDR_14

          ISERDES.OVERSAMPLE.DDR.W4 = OVERSAMPLE_DDR_4

          ISERDES.NUM_CE.N1 = NUM_CE_N1
          ISERDES.NUM_CE.N2 = NUM_CE_N2

          IFFDELMUXE3.P0 = IOBDELAY_IFD
          IDELMUXE3.P0 = IOBDELAY_IBUF

          IFF.ZINIT_Q1 = ZINIT_Q1
          IFF.ZINIT_Q2 = ZINIT_Q2
          IFF.ZINIT_Q3 = ZINIT_Q3
          IFF.ZINIT_Q4 = ZINIT_Q4

          IFF.ZSRVAL_Q1 = ZSRVAL_Q1
          IFF.ZSRVAL_Q2 = ZSRVAL_Q2
          IFF.ZSRVAL_Q3 = ZSRVAL_Q3
          IFF.ZSRVAL_Q4 = ZSRVAL_Q4

          IFF.ZINV_C = ZINV_C

          ZINV_D = ZINV_D
        </meta>
      </metadata>
    </pb_type>
    <interconnect>
      <direct name="BITSLIP" input="ILOGICE3.BITSLIP" output="ISERDESE2_IDELAY.BITSLIP"/>
      <direct name="CE1" input="ILOGICE3.CE1" output="ISERDESE2_IDELAY.CE1"/>
      <direct name="CE2" input="ILOGICE3.CE2" output="ISERDESE2_IDELAY.CE2"/>
      <direct name="CLK" input="ILOGICE3.CLK" output="ISERDESE2_IDELAY.CLK"/>
      <direct name="CLKB" input="ILOGICE3.CLKB" output="ISERDESE2_IDELAY.CLKB"/>
      <direct name="CLKDIV" input="ILOGICE3.CLKDIV" output="ISERDESE2_IDELAY.CLKDIV"/>
      <direct name="DDLY" input="ILOGICE3.DDLY" output="ISERDESE2_IDELAY.DDLY"/>
      <direct name="DYNCLKDIVPSEL" input="ILOGICE3.DYNCLKDIVPSEL" output="ISERDESE2_IDELAY.DYNCLKDIVPSEL"/>
      <direct name="DYNCLKDIVSEL" input="ILOGICE3.DYNCLKDIVSEL" output="ISERDESE2_IDELAY.DYNCLKDIVSEL"/>
      <direct name="DYNCLKSEL" input="ILOGICE3.DYNCLKSEL" output="ISERDESE2_IDELAY.DYNCLKSEL"/>
      <direct name="OCLK" input="ILOGICE3.OCLK" output="ISERDESE2_IDELAY.OCLK"/>
      <direct name="OCLKB" input="ILOGICE3.OCLKB" output="ISERDESE2_IDELAY.OCLKB"/>
      <direct name="OFB" input="ILOGICE3.OFB" output="ISERDESE2_IDELAY.OFB"/>
      <direct name="SHIFTIN1" input="ILOGICE3.SHIFTIN1" output="ISERDESE2_IDELAY.SHIFTIN1"/>
      <direct name="SHIFTIN2" input="ILOGICE3.SHIFTIN2" output="ISERDESE2_IDELAY.SHIFTIN2"/>
      <direct name="SR" input="ILOGICE3.SR" output="ISERDESE2_IDELAY.RST"/>
      <direct name="TFB" input="ILOGICE3.TFB" output="ISERDESE2_IDELAY.TFB"/>
      <direct name="O" input="ISERDESE2_IDELAY.O" output="ILOGICE3.O"/>
      <direct name="Q1" input="ISERDESE2_IDELAY.Q1" output="ILOGICE3.Q1"/>
      <direct name="Q2" input="ISERDESE2_IDELAY.Q2" output="ILOGICE3.Q2"/>
      <direct name="Q3" input="ISERDESE2_IDELAY.Q3" output="ILOGICE3.Q3"/>
      <direct name="Q4" input="ISERDESE2_IDELAY.Q4" output="ILOGICE3.Q4"/>
      <direct name="Q5" input="ISERDESE2_IDELAY.Q5" output="ILOGICE3.Q5"/>
      <direct name="Q6" input="ISERDESE2_IDELAY.Q6" output="ILOGICE3.Q6"/>
      <direct name="Q7" input="ISERDESE2_IDELAY.Q7" output="ILOGICE3.Q7"/>
      <direct name="Q8" input="ISERDESE2_IDELAY.Q8" output="ILOGICE3.Q8"/>
      <direct name="SHIFTOUT1" input="ISERDESE2_IDELAY.SHIFTOUT1" output="ILOGICE3.SHIFTOUT1"/>
      <direct name="SHIFTOUT2" input="ISERDESE2_IDELAY.SHIFTOUT2" output="ILOGICE3.SHIFTOUT2"/>
    </interconnect>
  </mode>

  <!-- ILOGICE3 hosting an IDDR primitive -->
  <mode name="ILOGIC">
    <pb_type name="IFF" blif_model=".subckt IDDR_VPR" num_pb="1">
      <clock  name="CK"  num_pins="1"/>
      <clock  name="CKB" num_pins="1"/>
      <input  name="CE"  num_pins="1"/>
      <input  name="SR"  num_pins="1"/>
      <input  name="D"   num_pins="1"/>
      <output name="Q1"  num_pins="1"/>
      <output name="Q2"  num_pins="1"/>

      <T_setup port="D" clock="CK" value="{setup_CK_D}"/>
      <T_hold  port="D" clock="CK" value="{hold_CK_D}"/>

      <T_setup port="CE" clock="CK" value="{setup_CK_D}"/>
      <T_hold  port="CE" clock="CK" value="{hold_CK_D}"/>

      <T_clock_to_Q port="Q1" clock="CK" max="{iopath_CLK_Q1}"/>
      <T_clock_to_Q port="Q2" clock="CK" max="{iopath_CLK_Q2}"/>

      <metadata>
        <meta name="fasm_features">
          IDDR_OR_ISERDES.IN_USE
        </meta>
        <meta name="fasm_params">
          ZINV_D = ZINV_D
          IFF.ZINV_C = ZINV_C
          IFF.SRTYPE.SYNC = SRTYPE_SYNC
          IFF.DDR_CLK_EDGE.SAME_EDGE = SAME_EDGE
          IFF.DDR_CLK_EDGE.OPPOSITE_EDGE = OPPOSITE_EDGE
          IFF.ZINIT_Q1 = ZINIT_Q1
          IFF.ZINIT_Q2 = ZINIT_Q2
          IFF.ZINIT_Q3 = ZINIT_Q3
          IFF.ZINIT_Q4 = ZINIT_Q4
          IFF.ZSRVAL_Q1 = ZSRVAL_Q12
          IFF.ZSRVAL_Q2 = ZSRVAL_Q12
          IFF.ZSRVAL_Q3 = ZSRVAL_Q34
          IFF.ZSRVAL_Q4 = ZSRVAL_Q34
        </meta>
      </metadata>
    </pb_type>

    <interconnect>

      <!-- Input connections -->
      <mux name="IFFDELMUX" input="ILOGICE3.DDLY ILOGICE3.D" output="IFF.D">
        <metadata>
          <meta name="fasm_mux">
            ILOGICE3.DDLY : IFFDELMUXE3.P0
            ILOGICE3.D : NULL
          </meta>
        </metadata>
      </mux>
      <direct name="ILOGICE3.CLK_to_IFF.CK" input="ILOGICE3.CLK" output="IFF.CK"/>
      <direct name="ILOGICE3.CLKB_to_IFF.CKB" input="ILOGICE3.CLKB" output="IFF.CKB"/>
      <direct name="ILOGICE3.CE1_to_IFF.CE" input="ILOGICE3.CE1" output="IFF.CE"/>
      <direct name="ILOGICE3.SR_to_IFF.SR" input="ILOGICE3.SR" output="IFF.SR"/>

      <!-- Output connections -->
      <direct name="IFF.Q1_to_ILOGICE3.Q1" input="IFF.Q1" output="ILOGICE3.Q1"/>
      <direct name="IFF.Q2_to_ILOGICE3.Q2" input="IFF.Q2" output="ILOGICE3.Q2"/>

      <!-- NOTE: There is a connection from ILOGICE3.D/ILOGICE3.DDLY bypassing
           the IDDR but it goes through an inverter controlled by it. Hence it
           is disabled -->

    </interconnect>
  </mode>

</pb_type>

Model XML

<models xmlns:xi="http://www.w3.org/2001/XInclude">
  <model name="ISERDESE2_NO_IDELAY_VPR">
    <input_ports>
      <port is_clock="1" name="CLK"/>
      <port is_clock="1" name="CLKB"/>
      <port is_clock="1" name="CLKDIV"/>
      <port clock="CLKDIV" name="BITSLIP"/>
      <!-- This is only correct for NUM_CE = 2 -->
      <port clock="CLKDIV" name="CE1"/>
      <port clock="CLKDIV" name="CE2"/>
      <port clock="CLK" combinational_sink_ports="O" name="D"/>
      <port name="DYNCLKDIVPSEL"/>
      <port name="DYNCLKDIVSEL"/>
      <port name="DYNCLKSEL"/>
      <port is_clock="1" name="OCLK"/>
      <port is_clock="1" name="OCLKB"/>
      <port clock="CLK" name="OFB" combinational_sink_ports="O"/>
      <port name="SHIFTIN1"/>
      <port name="SHIFTIN2"/>
      <port clock="CLKDIV" name="RST"/>
      <port combinational_sink_ports="O" name="TFB"/>
    </input_ports>
    <output_ports>
      <port name="O"/>
      <port clock="CLKDIV" name="Q1"/>
      <port clock="CLKDIV" name="Q2"/>
      <port clock="CLKDIV" name="Q3"/>
      <port clock="CLKDIV" name="Q4"/>
      <port clock="CLKDIV" name="Q5"/>
      <port clock="CLKDIV" name="Q6"/>
      <port clock="CLKDIV" name="Q7"/>
      <port clock="CLKDIV" name="Q8"/>
      <port name="SHIFTOUT1"/>
      <port name="SHIFTOUT2"/>
    </output_ports>
  </model>
  <model name="ISERDESE2_IDELAY_VPR">
    <input_ports>
      <port is_clock="1" name="CLK"/>
      <port is_clock="1" name="CLKB"/>
      <port is_clock="1" name="CLKDIV"/>
      <port clock="CLKDIV" name="BITSLIP"/>
      <port clock="CLKDIV" name="CE1"/>
      <port clock="CLKDIV" name="CE2"/>
      <port clock="CLK" combinational_sink_ports="O" name="DDLY"/>
      <port name="DYNCLKDIVPSEL"/>
      <port name="DYNCLKDIVSEL"/>
      <port name="DYNCLKSEL"/>
      <port is_clock="1" name="OCLK"/>
      <port is_clock="1" name="OCLKB"/>
      <port clock="CLK" name="OFB" combinational_sink_ports="O"/>
      <port name="SHIFTIN1"/>
      <port name="SHIFTIN2"/>
      <port clock="CLKDIV" name="RST"/>
      <port combinational_sink_ports="O" name="TFB"/>
    </input_ports>
    <output_ports>
      <port name="O"/>
      <port clock="CLKDIV" name="Q1"/>
      <port clock="CLKDIV" name="Q2"/>
      <port clock="CLKDIV" name="Q3"/>
      <port clock="CLKDIV" name="Q4"/>
      <port clock="CLKDIV" name="Q5"/>
      <port clock="CLKDIV" name="Q6"/>
      <port clock="CLKDIV" name="Q7"/>
      <port clock="CLKDIV" name="Q8"/>
      <port name="SHIFTOUT1"/>
      <port name="SHIFTOUT2"/>
    </output_ports>
  </model>
  <model name="IDDR_VPR">
    <input_ports>
      <port name="CK"  is_clock="1"/>
      <port name="CKB" is_clock="1"/>
      <port name="CE"  clock="CK"/>
      <port name="SR"/>
      <port name="D"   clock="CK"/>      
    </input_ports>
    <output_ports>
      <port name="Q1"  clock="CK"/>
      <port name="Q2"  clock="CK"/>
    </output_ports>
  </model>
</models>