srlc32e_vpr¶

Physical Block XML¶

<pb_type name="SRLC32E_VPR" num_pb="1" blif_model=".subckt SRLC32E_VPR" xmlns:xi="http://www.w3.org/2001/XInclude">
  <clock name="CLK" num_pins="1"/>
  <input name="CE" num_pins="1"/>  
  <input name="A" num_pins="5"/>  
  <input name="D" num_pins="1"/>  
  <output name="Q" num_pins="1"/>
  <output name="Q31" num_pins="1"/>

  <T_setup port="CE" clock="CLK" value="{setup_CLK_WE}"/>
  <T_hold port="CE" clock="CLK" value="{hold_CLK_WE}"/>
  <T_setup port="D" clock="CLK" value="{setup_CLK_DI1}"/>
  <T_hold port="D" clock="CLK" value="{hold_CLK_DI1}"/>

  <!-- Physically inputs A2-A6 of a LUT in SRL32 mode are used. Hence
       timings for those inputs are selected here -->      
  <delay_matrix type="min" in_port="A" out_port="Q">
    {iopath_A2_O6}
    {iopath_A3_O6}
    {iopath_A4_O6}
    {iopath_A5_O6}
    {iopath_A6_O6}
  </delay_matrix>

  <delay_matrix type="max" in_port="A" out_port="Q">
    {iopath_A2_O6}
    {iopath_A3_O6}
    {iopath_A4_O6}
    {iopath_A5_O6}
    {iopath_A6_O6}
  </delay_matrix>

  <!-- <T_clock_to_Q port="Q" clock="CLK" max="{iopath_CLK_O6}"/> -->
  <T_clock_to_Q port="Q31" clock="CLK" max="{iopath_CLK_MC31}"/>

  <metadata>
    <meta name="fasm_params">
      INIT[63:0] = INIT
    </meta>
    <meta name="fasm_features">
      SRL
    </meta>
  </metadata>

</pb_type>

Model XML¶

<!-- vim: set ai sw=1 ts=1 sta et: -->
<models xmlns:xi="http://www.w3.org/2001/XInclude">
 <model name="SRLC32E_VPR">
  <input_ports>
   <port name="CLK" is_clock="1"/>
   <port name="CE" clock="CLK"/>
   <port name="A" combinational_sink_ports="Q"/>
   <port name="D" clock="CLK"/>
  </input_ports>
  <output_ports>
   <!-- <port name="Q" clock="CLK"/> -->
   <port name="Q"/>
   <port name="Q31" clock="CLK"/>
  </output_ports>
 </model>
</models>