dffs¶

Physical Block XML¶

<!-- set: ai sw=1 ts=1 sta et -->
<!-- Flip flop found inside the iCE40 -->
<pb_type name="DFF" num_pb="1">
 <clock  name="C" num_pins="1"/>
 <input  name="E" num_pins="1"/>
 <input  name="S" num_pins="1"/>
 <input  name="D" num_pins="1"/>
 <output name="Q" num_pins="1"/>

 <!-- module SB_DFFSR (output Q, input C, R, D); -->
 <mode name="SB_DFFSR">
  <pb_type name="SB_DFFSR" num_pb="1" blif_model=".subckt SB_DFFSR">
   <output name="Q" num_pins="1"/>
   <clock  name="C" num_pins="1"/>
   <input  name="R" num_pins="1"/>
   <input  name="D" num_pins="1"/>
   <T_clock_to_Q max="10e-12" port="Q" clock="C"/>
   <T_setup    value="10e-12" port="R" clock="C"/>
   <T_setup    value="10e-12" port="D" clock="C"/>
  </pb_type>
  <interconnect>
   <direct><port type="input" from="SB_DFFSR" name="Q"/><port type="output" name="Q"/></direct>
   <direct><port type="input" name="C"/><port type="output" from="SB_DFFSR" name="C"/></direct>
   <direct><port type="input" name="S"/><port type="output" from="SB_DFFSR" name="R"/></direct>
   <direct><port type="input" name="D"/><port type="output" from="SB_DFFSR" name="D"/></direct>
  </interconnect>
 </mode>

 <!-- module SB_DFFR (output Q, input C, R, D); -->
 <mode name="SB_DFFR">
  <pb_type name="SB_DFFR" num_pb="1" blif_model=".subckt SB_DFFR">
   <output name="Q" num_pins="1"/>
   <clock  name="C" num_pins="1"/>
   <input  name="R" num_pins="1"/>
   <input  name="D" num_pins="1"/>
   <T_clock_to_Q max="10e-12" port="Q" clock="C"/>
   <T_setup    value="10e-12" port="R" clock="C"/>
   <T_setup    value="10e-12" port="D" clock="C"/>
  </pb_type>
  <interconnect>
   <direct><port type="input" from="SB_DFFR" name="Q"/><port type="output" name="Q"/></direct>
   <direct><port type="input" name="C"/><port type="output" from="SB_DFFR" name="C"/></direct>
   <direct><port type="input" name="S"/><port type="output" from="SB_DFFR" name="R"/></direct>
   <direct><port type="input" name="D"/><port type="output" from="SB_DFFR" name="D"/></direct>
  </interconnect>
 </mode>

 <!-- module SB_DFFSS (output Q, input C, S, D); -->
 <mode name="SB_DFFSS">
  <pb_type name="SB_DFFSS" num_pb="1" blif_model=".subckt SB_DFFSS">
   <output name="Q" num_pins="1"/>
   <clock  name="C" num_pins="1"/>
   <input  name="S" num_pins="1"/>
   <input  name="D" num_pins="1"/>
   <T_clock_to_Q max="10e-12" port="Q" clock="C"/>
   <T_setup    value="10e-12" port="S" clock="C"/>
   <T_setup    value="10e-12" port="D" clock="C"/>
  </pb_type>
  <interconnect>
   <direct><port type="input" from="SB_DFFSS" name="Q"/><port type="output" name="Q"/></direct>
   <direct><port type="input" name="C"/><port type="output" from="SB_DFFSS" name="C"/></direct>
   <direct><port type="input" name="S"/><port type="output" from="SB_DFFSS" name="S"/></direct>
   <direct><port type="input" name="D"/><port type="output" from="SB_DFFSS" name="D"/></direct>
  </interconnect>
 </mode>

 <!-- module SB_DFFS (output Q, input C, S, D); -->
 <mode name="SB_DFFS">
  <pb_type name="SB_DFFS" num_pb="1" blif_model=".subckt SB_DFFS">
   <output name="Q" num_pins="1"/>
   <clock  name="C" num_pins="1"/>
   <input  name="S" num_pins="1"/>
   <input  name="D" num_pins="1"/>
   <T_clock_to_Q max="10e-12" port="Q" clock="C"/>
   <T_setup    value="10e-12" port="S" clock="C"/>
   <T_setup    value="10e-12" port="D" clock="C"/>
  </pb_type>
  <interconnect>
   <direct><port type="input" from="SB_DFFS" name="Q"/><port type="output" name="Q"/></direct>
   <direct><port type="input" name="C"/><port type="output" from="SB_DFFS" name="C"/></direct>
   <direct><port type="input" name="S"/><port type="output" from="SB_DFFS" name="S"/></direct>
   <direct><port type="input" name="D"/><port type="output" from="SB_DFFS" name="D"/></direct>
  </interconnect>
 </mode>
</pb_type>