symbiflow-arch-defs

Table Of Contents

srusedmux

Component Diagram

Internal Diagram

Verilog File

`include "../../../../../../vpr/muxes/logic/mux2/mux2.sim.v"

module SRUSEDMUX(IN, OUT);
	input wire IN;

	parameter S = 0;
	output wire OUT;

	MUX2 mux (
		.I0(0),
		.I1(IN),
		.S0(S),
		.O(OUT)
	);
endmodule

Physical Block XML

<pb_type name="AFFMUX" num_pb="1">
  <!--
Generated with ../../../../../utils/mux_gen.py
-->
  <input name="XOR" num_pins="1"/>
  <input name="O6" num_pins="1"/>
  <input name="O5" num_pins="1"/>
  <input name="F7" num_pins="1"/>
  <input name="CY" num_pins="1"/>
  <input name="AX" num_pins="1"/>
  <output name="O" num_pins="1"/>
  <interconnect>
    <mux input="AFFMUX.XOR AFFMUX.O6 AFFMUX.O5 AFFMUX.F7 AFFMUX.CY AFFMUX.AX" name="_AFFMUX" output="AFFMUX.O"/>
  </interconnect>
</pb_type>

Table Of Contents

• srusedmux
  • Component Diagram
  • Internal Diagram
  • Verilog File
  • Physical Block XML

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