symbiflow-arch-defs
symbiflow-arch-defs

L6MUX21

Component Diagram

`default_nettype none module L6MUX21 (input D0, D1, SD, output Z); assign Z = SD ? D1 : D0; endmodule

Internal Diagram

/home/docs/checkouts/readthedocs.org/user_builds/rw1nkler-symbiflow-arch-defs/checkouts/latest/ecp5/primitives/slice/L6MUX21/L6MUX21.sim.v

Verilog File

`default_nettype none
module L6MUX21 (input D0, D1, SD, output Z);
	assign Z = SD ? D1 : D0;
endmodule