rambfifo36e1¶
Physical Block XML¶
<!-- vim: set ai sw=1 ts=1 sta et: -->
<!--
Block RAM in 7 series is 36kbbit split into two 18kbit sections.
The Block RAM is "true dual port".
There are both Latches (first) and Registers (second) on the output (why!?)
The RAM has extra bits that can be used for parity (DIP / DOP).
-->
<pb_type name="RAMBFIFO36E1" num_pb="1">
<input name="WEBWEU" num_pins="8" />
<input name="WEBWEL" num_pins="8" />
<input name="WEAU" num_pins="4" />
<input name="WEAL" num_pins="4" />
<input name="TSTWROS" num_pins="13" />
<input name="TSTWRCNTOFF" num_pins="1" />
<input name="TSTRDOS" num_pins="13" />
<input name="TSTRDCNTOFF" num_pins="1" />
<input name="TSTOFF" num_pins="1" />
<input name="TSTIN" num_pins="5" />
<input name="TSTFLAGIN" num_pins="1" />
<input name="TSTCNT" num_pins="13" />
<input name="TSTBRAMRST" num_pins="1" />
<input name="RSTREGBU" num_pins="1" />
<input name="RSTREGBL" num_pins="1" />
<input name="RSTREGARSTREGU" num_pins="1" />
<input name="RSTREGARSTREGL" num_pins="1" />
<input name="RSTRAMBU" num_pins="1" />
<input name="RSTRAMBL" num_pins="1" />
<input name="RSTRAMARSTRAMU" num_pins="1" />
<input name="RSTRAMARSTRAMLRST" num_pins="1" />
<input name="REGCLKBU" num_pins="1" />
<input name="REGCLKBL" num_pins="1" />
<input name="REGCLKARDRCLKU" num_pins="1" />
<input name="REGCLKARDRCLKL" num_pins="1" />
<input name="REGCEBU" num_pins="1" />
<input name="REGCEBL" num_pins="1" />
<input name="REGCEAREGCEU" num_pins="1" />
<input name="REGCEAREGCEL" num_pins="1" />
<input name="INJECTDBITERR" num_pins="1" />
<input name="INJECTSBITERR" num_pins="1" />
<input name="ENBWRENU" num_pins="1" />
<input name="ENBWRENL" num_pins="1" />
<input name="ENARDENU" num_pins="1" />
<input name="ENARDENL" num_pins="1" />
<input name="DIPBDIP" num_pins="4" />
<input name="DIPADIP" num_pins="4" />
<input name="DIBDI" num_pins="32" />
<input name="DIADI" num_pins="32" />
<clock name="CLKBWRCLKU" num_pins="1" />
<clock name="CLKBWRCLKL" num_pins="1" />
<clock name="CLKARDCLKU" num_pins="1" />
<clock name="CLKARDCLKL" num_pins="1" />
<input name="CASCADEINA" num_pins="1" />
<input name="CASCADEINB" num_pins="1" />
<input name="ADDRBWRADDRU" num_pins="15" />
<input name="ADDRBWRADDRL" num_pins="16" />
<input name="ADDRARDADDRU" num_pins="15" />
<input name="ADDRARDADDRL" num_pins="16" />
<output name="WRERR" num_pins="1" />
<output name="WRCOUNT" num_pins="13" />
<output name="TSTOUT" num_pins="5" />
<output name="SBITERR" num_pins="1" />
<output name="RDERR" num_pins="1" />
<output name="RDCOUNT" num_pins="13" />
<output name="FULL" num_pins="1" />
<output name="EMPTY" num_pins="1" />
<output name="ECCPARITY" num_pins="8" />
<output name="DOPBDOP" num_pins="4" />
<output name="DOPADOP" num_pins="4" />
<output name="DOBDO" num_pins="32" />
<output name="DOADO" num_pins="32" />
<output name="DBITERR" num_pins="1" />
<output name="CASCADEOUTA" num_pins="1" />
<output name="CASCADEOUTB" num_pins="1" />
<output name="ALMOSTFULL" num_pins="1" />
<output name="ALMOSTEMPTY" num_pins="1" />
<!-- Missing FIFO36E1 -->
<mode name="BRAM">
<pb_type name="RAMB36E1" num_pb="1" blif_model=".subckt RAMB36E1_PRIM">
<!-- Port A - 32bit wide -->
<clock name="CLKARDCLKU" num_pins="1" />
<clock name="CLKARDCLKL" num_pins="1" />
<input name="REGCEAREGCEU" num_pins="1" />
<input name="REGCEAREGCEL" num_pins="1" />
<input name="REGCLKARDRCLKU" num_pins="1" />
<input name="REGCLKARDRCLKL" num_pins="1" />
<input name="ENARDENU" num_pins="1" />
<input name="ENARDENL" num_pins="1" />
<input name="RSTRAMARSTRAMU" num_pins="1" />
<input name="RSTRAMARSTRAMLRST" num_pins="1" />
<input name="RSTREGARSTREGU" num_pins="1" />
<input name="RSTREGARSTREGL" num_pins="1" />
<input name="ADDRARDADDRU" num_pins="15" />
<input name="ADDRARDADDRL" num_pins="16" />
<input name="DIADI" num_pins="32" />
<input name="DIPADIP" num_pins="4" />
<input name="WEAU" num_pins="4" />
<input name="WEAL" num_pins="4" />
<output name="DOADO" num_pins="32" />
<output name="DOPADOP" num_pins="4" />
<T_setup value="{setup_CLKARDCLKL_REGCEAL}" port="REGCEAREGCEU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKL_REGCEAL}" port="REGCEAREGCEU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKL_REGCEAL}" port="REGCEAREGCEL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKL_REGCEAL}" port="REGCEAREGCEL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_ENARDENU}" port="ENARDENU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_ENARDENU}" port="ENARDENU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_ENARDENU}" port="ENARDENL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_ENARDENU}" port="ENARDENL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAMU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAMU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAMLRST" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAMLRST" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREGU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREGU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREGL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREGL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_ADDRAU}" port="ADDRARDADDRU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_ADDRAU}" port="ADDRARDADDRU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_ADDRA15L}" port="ADDRARDADDRL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_ADDRA15L}" port="ADDRARDADDRL" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_DIADIU}" port="DIADI" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_DIADIU}" port="DIADI" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_DIPADIPU}" port="DIPADIP" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_DIPADIPU}" port="DIPADIP" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_WEAU}" port="WEAU" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_WEAU}" port="WEAU" clock="CLKARDCLKL" />
<T_setup value="{setup_CLKARDCLKU_WEAU}" port="WEAL" clock="CLKARDCLKL" />
<T_hold value="{hold_CLKARDCLKU_WEAU}" port="WEAL" clock="CLKARDCLKL" />
<T_clock_to_Q max="{iopath_CLKARDCLKU_DOADOU}" port="DOADO" clock="CLKARDCLKL" />
<T_clock_to_Q max="{iopath_CLKARDCLKU_DOPADOPU}" port="DOPADOP" clock="CLKARDCLKL" />
<!-- Fake timing values as there is no database entry for these i/o -->
<T_setup value="10e-12" port="REGCLKARDRCLKU" clock="CLKARDCLKL" />
<T_setup value="10e-12" port="REGCLKARDRCLKL" clock="CLKARDCLKL" />
<!-- Port B - 32bit wide -->
<clock name="CLKBWRCLKU" num_pins="1" />
<clock name="CLKBWRCLKL" num_pins="1" />
<input name="ENBWRENU" num_pins="1" />
<input name="ENBWRENL" num_pins="1" />
<input name="REGCEBU" num_pins="1" />
<input name="REGCEBL" num_pins="1" />
<input name="REGCLKBU" num_pins="1" />
<input name="REGCLKBL" num_pins="1" />
<input name="RSTRAMBU" num_pins="1" />
<input name="RSTRAMBL" num_pins="1" />
<input name="RSTREGBU" num_pins="1" />
<input name="RSTREGBL" num_pins="1" />
<input name="ADDRBWRADDRU" num_pins="15" />
<input name="ADDRBWRADDRL" num_pins="16" />
<input name="DIBDI" num_pins="32" />
<input name="DIPBDIP" num_pins="4" />
<input name="WEBWEU" num_pins="8" />
<input name="WEBWEL" num_pins="8" />
<output name="DOBDO" num_pins="32" />
<output name="DOPBDOP" num_pins="4" />
<T_setup value="{setup_CLKBWRCLKU_ENBWRENU}" port="ENBWRENU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_ENBWRENU}" port="ENBWRENU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_ENBWRENU}" port="ENBWRENL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_ENBWRENU}" port="ENBWRENL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_REGCEBU}" port="REGCEBU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_REGCEBU}" port="REGCEBU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_REGCEBU}" port="REGCEBL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_REGCEBU}" port="REGCEBL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMBU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMBU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMBL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMBL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_RSTREGBU}" port="RSTREGBU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_RSTREGBU}" port="RSTREGBU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_RSTREGBU}" port="RSTREGBL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_RSTREGBU}" port="RSTREGBL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_ADDRBU}" port="ADDRBWRADDRU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_ADDRBU}" port="ADDRBWRADDRU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_ADDRB15L}" port="ADDRBWRADDRL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_ADDRB15L}" port="ADDRBWRADDRL" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_DIBDIU}" port="DIBDI" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_DIBDIU}" port="DIBDI" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_DIPBDIPU}" port="DIPBDIP" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_DIPBDIPU}" port="DIPBDIP" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_WEBU}" port="WEBWEU" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_WEBU}" port="WEBWEU" clock="CLKBWRCLKL" />
<T_setup value="{setup_CLKBWRCLKU_WEBU}" port="WEBWEL" clock="CLKBWRCLKL" />
<T_hold value="{hold_CLKBWRCLKU_WEBU}" port="WEBWEL" clock="CLKBWRCLKL" />
<T_clock_to_Q max="{iopath_CLKBWRCLKU_DOBDOU}" port="DOBDO" clock="CLKBWRCLKL" />
<T_clock_to_Q max="{iopath_CLKBWRCLKU_DOPBDOPU}" port="DOPBDOP" clock="CLKBWRCLKL" />
<!-- Fake timing values as there is no database entry for these i/o -->
<T_setup value="10e-12" port="REGCLKBU" clock="CLKBWRCLKL" />
<T_setup value="10e-12" port="REGCLKBL" clock="CLKBWRCLKL" />
<input name="CASCADEINA" num_pins="1" />
<input name="CASCADEINB" num_pins="1" />
<output name="CASCADEOUTA" num_pins="1" />
<output name="CASCADEOUTB" num_pins="1" />
<metadata>
<meta name="fasm_params">
RAMB18_Y0.IN_USE = IN_USE
RAMB18_Y1.IN_USE = IN_USE
RAMB18_Y0.ZINIT_A[17:0] = ZINIT_A[17:0]
RAMB18_Y0.ZINIT_B[17:0] = ZINIT_B[17:0]
RAMB18_Y1.ZINIT_A[17:0] = ZINIT_A[35:18]
RAMB18_Y1.ZINIT_B[17:0] = ZINIT_B[35:18]
RAMB18_Y0.ZSRVAL_A[17:0] = ZSRVAL_A[17:0]
RAMB18_Y0.ZSRVAL_B[17:0] = ZSRVAL_B[17:0]
RAMB18_Y1.ZSRVAL_A[17:0] = ZSRVAL_A[35:18]
RAMB18_Y1.ZSRVAL_B[17:0] = ZSRVAL_B[35:18]
RAMB18_Y0.INITP_00[255:0] = INITP_00
RAMB18_Y0.INITP_01[255:0] = INITP_01
RAMB18_Y0.INITP_02[255:0] = INITP_02
RAMB18_Y0.INITP_03[255:0] = INITP_03
RAMB18_Y0.INITP_04[255:0] = INITP_04
RAMB18_Y0.INITP_05[255:0] = INITP_05
RAMB18_Y0.INITP_06[255:0] = INITP_06
RAMB18_Y0.INITP_07[255:0] = INITP_07
RAMB18_Y1.INITP_00[255:0] = INITP_08
RAMB18_Y1.INITP_01[255:0] = INITP_09
RAMB18_Y1.INITP_02[255:0] = INITP_0A
RAMB18_Y1.INITP_03[255:0] = INITP_0B
RAMB18_Y1.INITP_04[255:0] = INITP_0C
RAMB18_Y1.INITP_05[255:0] = INITP_0D
RAMB18_Y1.INITP_06[255:0] = INITP_0E
RAMB18_Y1.INITP_07[255:0] = INITP_0F
RAMB18_Y0.INIT_00[255:0] = INIT_00
RAMB18_Y0.INIT_01[255:0] = INIT_01
RAMB18_Y0.INIT_02[255:0] = INIT_02
RAMB18_Y0.INIT_03[255:0] = INIT_03
RAMB18_Y0.INIT_04[255:0] = INIT_04
RAMB18_Y0.INIT_05[255:0] = INIT_05
RAMB18_Y0.INIT_06[255:0] = INIT_06
RAMB18_Y0.INIT_07[255:0] = INIT_07
RAMB18_Y0.INIT_08[255:0] = INIT_08
RAMB18_Y0.INIT_09[255:0] = INIT_09
RAMB18_Y0.INIT_0A[255:0] = INIT_0A
RAMB18_Y0.INIT_0B[255:0] = INIT_0B
RAMB18_Y0.INIT_0C[255:0] = INIT_0C
RAMB18_Y0.INIT_0D[255:0] = INIT_0D
RAMB18_Y0.INIT_0E[255:0] = INIT_0E
RAMB18_Y0.INIT_0F[255:0] = INIT_0F
RAMB18_Y0.INIT_10[255:0] = INIT_10
RAMB18_Y0.INIT_11[255:0] = INIT_11
RAMB18_Y0.INIT_12[255:0] = INIT_12
RAMB18_Y0.INIT_13[255:0] = INIT_13
RAMB18_Y0.INIT_14[255:0] = INIT_14
RAMB18_Y0.INIT_15[255:0] = INIT_15
RAMB18_Y0.INIT_16[255:0] = INIT_16
RAMB18_Y0.INIT_17[255:0] = INIT_17
RAMB18_Y0.INIT_18[255:0] = INIT_18
RAMB18_Y0.INIT_19[255:0] = INIT_19
RAMB18_Y0.INIT_1A[255:0] = INIT_1A
RAMB18_Y0.INIT_1B[255:0] = INIT_1B
RAMB18_Y0.INIT_1C[255:0] = INIT_1C
RAMB18_Y0.INIT_1D[255:0] = INIT_1D
RAMB18_Y0.INIT_1E[255:0] = INIT_1E
RAMB18_Y0.INIT_1F[255:0] = INIT_1F
RAMB18_Y0.INIT_20[255:0] = INIT_20
RAMB18_Y0.INIT_21[255:0] = INIT_21
RAMB18_Y0.INIT_22[255:0] = INIT_22
RAMB18_Y0.INIT_23[255:0] = INIT_23
RAMB18_Y0.INIT_24[255:0] = INIT_24
RAMB18_Y0.INIT_25[255:0] = INIT_25
RAMB18_Y0.INIT_26[255:0] = INIT_26
RAMB18_Y0.INIT_27[255:0] = INIT_27
RAMB18_Y0.INIT_28[255:0] = INIT_28
RAMB18_Y0.INIT_29[255:0] = INIT_29
RAMB18_Y0.INIT_2A[255:0] = INIT_2A
RAMB18_Y0.INIT_2B[255:0] = INIT_2B
RAMB18_Y0.INIT_2C[255:0] = INIT_2C
RAMB18_Y0.INIT_2D[255:0] = INIT_2D
RAMB18_Y0.INIT_2E[255:0] = INIT_2E
RAMB18_Y0.INIT_2F[255:0] = INIT_2F
RAMB18_Y0.INIT_30[255:0] = INIT_30
RAMB18_Y0.INIT_31[255:0] = INIT_31
RAMB18_Y0.INIT_32[255:0] = INIT_32
RAMB18_Y0.INIT_33[255:0] = INIT_33
RAMB18_Y0.INIT_34[255:0] = INIT_34
RAMB18_Y0.INIT_35[255:0] = INIT_35
RAMB18_Y0.INIT_36[255:0] = INIT_36
RAMB18_Y0.INIT_37[255:0] = INIT_37
RAMB18_Y0.INIT_38[255:0] = INIT_38
RAMB18_Y0.INIT_39[255:0] = INIT_39
RAMB18_Y0.INIT_3A[255:0] = INIT_3A
RAMB18_Y0.INIT_3B[255:0] = INIT_3B
RAMB18_Y0.INIT_3C[255:0] = INIT_3C
RAMB18_Y0.INIT_3D[255:0] = INIT_3D
RAMB18_Y0.INIT_3E[255:0] = INIT_3E
RAMB18_Y0.INIT_3F[255:0] = INIT_3F
RAMB18_Y1.INIT_00[255:0] = INIT_40
RAMB18_Y1.INIT_01[255:0] = INIT_41
RAMB18_Y1.INIT_02[255:0] = INIT_42
RAMB18_Y1.INIT_03[255:0] = INIT_43
RAMB18_Y1.INIT_04[255:0] = INIT_44
RAMB18_Y1.INIT_05[255:0] = INIT_45
RAMB18_Y1.INIT_06[255:0] = INIT_46
RAMB18_Y1.INIT_07[255:0] = INIT_47
RAMB18_Y1.INIT_08[255:0] = INIT_48
RAMB18_Y1.INIT_09[255:0] = INIT_49
RAMB18_Y1.INIT_0A[255:0] = INIT_4A
RAMB18_Y1.INIT_0B[255:0] = INIT_4B
RAMB18_Y1.INIT_0C[255:0] = INIT_4C
RAMB18_Y1.INIT_0D[255:0] = INIT_4D
RAMB18_Y1.INIT_0E[255:0] = INIT_4E
RAMB18_Y1.INIT_0F[255:0] = INIT_4F
RAMB18_Y1.INIT_10[255:0] = INIT_50
RAMB18_Y1.INIT_11[255:0] = INIT_51
RAMB18_Y1.INIT_12[255:0] = INIT_52
RAMB18_Y1.INIT_13[255:0] = INIT_53
RAMB18_Y1.INIT_14[255:0] = INIT_54
RAMB18_Y1.INIT_15[255:0] = INIT_55
RAMB18_Y1.INIT_16[255:0] = INIT_56
RAMB18_Y1.INIT_17[255:0] = INIT_57
RAMB18_Y1.INIT_18[255:0] = INIT_58
RAMB18_Y1.INIT_19[255:0] = INIT_59
RAMB18_Y1.INIT_1A[255:0] = INIT_5A
RAMB18_Y1.INIT_1B[255:0] = INIT_5B
RAMB18_Y1.INIT_1C[255:0] = INIT_5C
RAMB18_Y1.INIT_1D[255:0] = INIT_5D
RAMB18_Y1.INIT_1E[255:0] = INIT_5E
RAMB18_Y1.INIT_1F[255:0] = INIT_5F
RAMB18_Y1.INIT_20[255:0] = INIT_60
RAMB18_Y1.INIT_21[255:0] = INIT_61
RAMB18_Y1.INIT_22[255:0] = INIT_62
RAMB18_Y1.INIT_23[255:0] = INIT_63
RAMB18_Y1.INIT_24[255:0] = INIT_64
RAMB18_Y1.INIT_25[255:0] = INIT_65
RAMB18_Y1.INIT_26[255:0] = INIT_66
RAMB18_Y1.INIT_27[255:0] = INIT_67
RAMB18_Y1.INIT_28[255:0] = INIT_68
RAMB18_Y1.INIT_29[255:0] = INIT_69
RAMB18_Y1.INIT_2A[255:0] = INIT_6A
RAMB18_Y1.INIT_2B[255:0] = INIT_6B
RAMB18_Y1.INIT_2C[255:0] = INIT_6C
RAMB18_Y1.INIT_2D[255:0] = INIT_6D
RAMB18_Y1.INIT_2E[255:0] = INIT_6E
RAMB18_Y1.INIT_2F[255:0] = INIT_6F
RAMB18_Y1.INIT_30[255:0] = INIT_70
RAMB18_Y1.INIT_31[255:0] = INIT_71
RAMB18_Y1.INIT_32[255:0] = INIT_72
RAMB18_Y1.INIT_33[255:0] = INIT_73
RAMB18_Y1.INIT_34[255:0] = INIT_74
RAMB18_Y1.INIT_35[255:0] = INIT_75
RAMB18_Y1.INIT_36[255:0] = INIT_76
RAMB18_Y1.INIT_37[255:0] = INIT_77
RAMB18_Y1.INIT_38[255:0] = INIT_78
RAMB18_Y1.INIT_39[255:0] = INIT_79
RAMB18_Y1.INIT_3A[255:0] = INIT_7A
RAMB18_Y1.INIT_3B[255:0] = INIT_7B
RAMB18_Y1.INIT_3C[255:0] = INIT_7C
RAMB18_Y1.INIT_3D[255:0] = INIT_7D
RAMB18_Y1.INIT_3E[255:0] = INIT_7E
RAMB18_Y1.INIT_3F[255:0] = INIT_7F
RAMB18_Y0.ZINV_CLKARDCLK = ZINV_CLKARDCLK
RAMB18_Y1.ZINV_CLKARDCLK = ZINV_CLKARDCLK
RAMB18_Y0.ZINV_CLKBWRCLK = ZINV_CLKBWRCLK
RAMB18_Y1.ZINV_CLKBWRCLK = ZINV_CLKBWRCLK
RAMB18_Y0.ZINV_ENARDEN = ZINV_ENARDEN
RAMB18_Y1.ZINV_ENARDEN = ZINV_ENARDEN
RAMB18_Y0.ZINV_ENBWREN = ZINV_ENBWREN
RAMB18_Y1.ZINV_ENBWREN = ZINV_ENBWREN
RAMB18_Y0.ZINV_RSTRAMARSTRAM = ZINV_RSTRAMARSTRAM
RAMB18_Y1.ZINV_RSTRAMARSTRAM = ZINV_RSTRAMARSTRAM
RAMB18_Y0.ZINV_RSTRAMB = ZINV_RSTRAMB
RAMB18_Y1.ZINV_RSTRAMB = ZINV_RSTRAMB
RAMB18_Y0.ZINV_RSTREGARSTREG = ZINV_RSTREGARSTREG
RAMB18_Y1.ZINV_RSTREGARSTREG = ZINV_RSTREGARSTREG
RAMB18_Y0.ZINV_RSTREGB = ZINV_RSTREGB
RAMB18_Y1.ZINV_RSTREGB = ZINV_RSTREGB
RAMB18_Y0.ZINV_REGCLKARDRCLK = ZINV_REGCLKARDRCLK
RAMB18_Y1.ZINV_REGCLKARDRCLK = ZINV_REGCLKARDRCLK
RAMB18_Y0.ZINV_REGCLKB = ZINV_REGCLKB
RAMB18_Y1.ZINV_REGCLKB = ZINV_REGCLKB
RAMB18_Y0.DOA_REG = DOA_REG
RAMB18_Y1.DOA_REG = DOA_REG
RAMB18_Y0.DOB_REG = DOB_REG
RAMB18_Y1.DOB_REG = DOB_REG
RAMB18_Y0.SDP_READ_WIDTH_36 = SDP_READ_WIDTH_36
RAMB18_Y0.READ_WIDTH_A_18 = READ_WIDTH_A_18
RAMB18_Y0.READ_WIDTH_A_9 = READ_WIDTH_A_9
RAMB18_Y0.READ_WIDTH_A_4 = READ_WIDTH_A_4
RAMB18_Y0.READ_WIDTH_A_2 = READ_WIDTH_A_2
RAMB18_Y0.READ_WIDTH_A_1 = READ_WIDTH_A_1
RAMB18_Y0.READ_WIDTH_B_18 = READ_WIDTH_B_18
RAMB18_Y0.READ_WIDTH_B_9 = READ_WIDTH_B_9
RAMB18_Y0.READ_WIDTH_B_4 = READ_WIDTH_B_4
RAMB18_Y0.READ_WIDTH_B_2 = READ_WIDTH_B_2
RAMB18_Y0.READ_WIDTH_B_1 = READ_WIDTH_B_1
RAMB18_Y0.SDP_WRITE_WIDTH_36 = SDP_WRITE_WIDTH_36
RAMB18_Y0.WRITE_WIDTH_A_18 = WRITE_WIDTH_A_18
RAMB18_Y0.WRITE_WIDTH_A_9 = WRITE_WIDTH_A_9
RAMB18_Y0.WRITE_WIDTH_A_4 = WRITE_WIDTH_A_4
RAMB18_Y0.WRITE_WIDTH_A_2 = WRITE_WIDTH_A_2
RAMB18_Y0.WRITE_WIDTH_A_1 = WRITE_WIDTH_A_1
RAMB18_Y0.WRITE_WIDTH_B_18 = WRITE_WIDTH_B_18
RAMB18_Y0.WRITE_WIDTH_B_9 = WRITE_WIDTH_B_9
RAMB18_Y0.WRITE_WIDTH_B_4 = WRITE_WIDTH_B_4
RAMB18_Y0.WRITE_WIDTH_B_2 = WRITE_WIDTH_B_2
RAMB18_Y0.WRITE_WIDTH_B_1 = WRITE_WIDTH_B_1
RAMB18_Y1.SDP_READ_WIDTH_36 = SDP_READ_WIDTH_36
RAMB18_Y1.READ_WIDTH_A_18 = READ_WIDTH_A_18
RAMB18_Y1.READ_WIDTH_A_9 = READ_WIDTH_A_9
RAMB18_Y1.READ_WIDTH_A_4 = READ_WIDTH_A_4
RAMB18_Y1.READ_WIDTH_A_2 = READ_WIDTH_A_2
RAMB18_Y1.READ_WIDTH_A_1 = READ_WIDTH_A_1
RAMB18_Y1.READ_WIDTH_B_18 = READ_WIDTH_B_18
RAMB18_Y1.READ_WIDTH_B_9 = READ_WIDTH_B_9
RAMB18_Y1.READ_WIDTH_B_4 = READ_WIDTH_B_4
RAMB18_Y1.READ_WIDTH_B_2 = READ_WIDTH_B_2
RAMB18_Y1.READ_WIDTH_B_1 = READ_WIDTH_B_1
RAMB18_Y1.SDP_WRITE_WIDTH_36 = SDP_WRITE_WIDTH_36
RAMB18_Y1.WRITE_WIDTH_A_18 = WRITE_WIDTH_A_18
RAMB18_Y1.WRITE_WIDTH_A_9 = WRITE_WIDTH_A_9
RAMB18_Y1.WRITE_WIDTH_A_4 = WRITE_WIDTH_A_4
RAMB18_Y1.WRITE_WIDTH_A_2 = WRITE_WIDTH_A_2
RAMB18_Y1.WRITE_WIDTH_A_1 = WRITE_WIDTH_A_1
RAMB18_Y1.WRITE_WIDTH_B_18 = WRITE_WIDTH_B_18
RAMB18_Y1.WRITE_WIDTH_B_9 = WRITE_WIDTH_B_9
RAMB18_Y1.WRITE_WIDTH_B_4 = WRITE_WIDTH_B_4
RAMB18_Y1.WRITE_WIDTH_B_2 = WRITE_WIDTH_B_2
RAMB18_Y1.WRITE_WIDTH_B_1 = WRITE_WIDTH_B_1
RAMB18_Y0.WRITE_MODE_A_NO_CHANGE = WRITE_MODE_A_NO_CHANGE
RAMB18_Y0.WRITE_MODE_A_READ_FIRST = WRITE_MODE_A_READ_FIRST
RAMB18_Y0.WRITE_MODE_B_NO_CHANGE = WRITE_MODE_B_NO_CHANGE
RAMB18_Y0.WRITE_MODE_B_READ_FIRST = WRITE_MODE_B_READ_FIRST
RAMB18_Y1.WRITE_MODE_A_NO_CHANGE = WRITE_MODE_A_NO_CHANGE
RAMB18_Y1.WRITE_MODE_A_READ_FIRST = WRITE_MODE_A_READ_FIRST
RAMB18_Y1.WRITE_MODE_B_NO_CHANGE = WRITE_MODE_B_NO_CHANGE
RAMB18_Y1.WRITE_MODE_B_READ_FIRST = WRITE_MODE_B_READ_FIRST
RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG = RSTREG_PRIORITY_A_RSTREG
RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG = RSTREG_PRIORITY_A_RSTREG
RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG = RSTREG_PRIORITY_B_RSTREG
RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG = RSTREG_PRIORITY_B_RSTREG
RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER = RAM_EXTENSION_A_NONE_OR_UPPER
RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER = RAM_EXTENSION_B_NONE_OR_UPPER
RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE = RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE
RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE = RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE
ZALMOST_EMPTY_OFFSET[12:0] = ZALMOST_EMPTY_OFFSET
ZALMOST_FULL_OFFSET[12:0] = ZALMOST_FULL_OFFSET
</meta>
<meta name="type">bel</meta>
<meta name="subtype">memory</meta>
</metadata>
</pb_type>
<interconnect>
<!-- Port A inputs -->
<direct name="CLKARDCLKU" input="RAMBFIFO36E1.CLKARDCLKU" output="RAMB36E1.CLKARDCLKU" />
<direct name="CLKARDCLKL" input="RAMBFIFO36E1.CLKARDCLKL" output="RAMB36E1.CLKARDCLKL" />
<direct name="REGCEAREGCEU" input="RAMBFIFO36E1.REGCEAREGCEU" output="RAMB36E1.REGCEAREGCEU" />
<direct name="REGCEAREGCEL" input="RAMBFIFO36E1.REGCEAREGCEL" output="RAMB36E1.REGCEAREGCEL" />
<direct name="REGCLKARDRCLKU" input="RAMBFIFO36E1.REGCLKARDRCLKU" output="RAMB36E1.REGCLKARDRCLKU" />
<direct name="REGCLKARDRCLKL" input="RAMBFIFO36E1.REGCLKARDRCLKL" output="RAMB36E1.REGCLKARDRCLKL" />
<direct name="ENARDENU" input="RAMBFIFO36E1.ENARDENU" output="RAMB36E1.ENARDENU" />
<direct name="ENARDENL" input="RAMBFIFO36E1.ENARDENL" output="RAMB36E1.ENARDENL" />
<direct name="RSTRAMARSTRAMU" input="RAMBFIFO36E1.RSTRAMARSTRAMU" output="RAMB36E1.RSTRAMARSTRAMU" />
<direct name="RSTRAMARSTRAMLRST" input="RAMBFIFO36E1.RSTRAMARSTRAMLRST" output="RAMB36E1.RSTRAMARSTRAMLRST" />
<direct name="RSTREGARSTREGU" input="RAMBFIFO36E1.RSTREGARSTREGU" output="RAMB36E1.RSTREGARSTREGU" />
<direct name="RSTREGARSTREGL" input="RAMBFIFO36E1.RSTREGARSTREGL" output="RAMB36E1.RSTREGARSTREGL" />
<direct name="ADDRARDADDRU" input="RAMBFIFO36E1.ADDRARDADDRU" output="RAMB36E1.ADDRARDADDRU" />
<direct name="ADDRARDADDRL" input="RAMBFIFO36E1.ADDRARDADDRL" output="RAMB36E1.ADDRARDADDRL" />
<direct name="DIADI" input="RAMBFIFO36E1.DIADI" output="RAMB36E1.DIADI" />
<direct name="DIPADIP" input="RAMBFIFO36E1.DIPADIP" output="RAMB36E1.DIPADIP" />
<direct name="WEAU" input="RAMBFIFO36E1.WEAU" output="RAMB36E1.WEAU" />
<direct name="WEAL" input="RAMBFIFO36E1.WEAL" output="RAMB36E1.WEAL" />
<!-- Port A outputs -->
<direct name="DOADO" input="RAMB36E1.DOADO" output="RAMBFIFO36E1.DOADO" />
<direct name="DOPADOP" input="RAMB36E1.DOPADOP" output="RAMBFIFO36E1.DOPADOP" />
<!-- Port B inputs -->
<direct name="CLKBWRCLKU" input="RAMBFIFO36E1.CLKBWRCLKU" output="RAMB36E1.CLKBWRCLKU" />
<direct name="CLKBWRCLKL" input="RAMBFIFO36E1.CLKBWRCLKL" output="RAMB36E1.CLKBWRCLKL" />
<direct name="ENBWRENU" input="RAMBFIFO36E1.ENBWRENU" output="RAMB36E1.ENBWRENU" />
<direct name="ENBWRENL" input="RAMBFIFO36E1.ENBWRENL" output="RAMB36E1.ENBWRENL" />
<direct name="REGCEBU" input="RAMBFIFO36E1.REGCEBU" output="RAMB36E1.REGCEBU" />
<direct name="REGCEBL" input="RAMBFIFO36E1.REGCEBL" output="RAMB36E1.REGCEBL" />
<direct name="REGCLKBU" input="RAMBFIFO36E1.REGCLKBU" output="RAMB36E1.REGCLKBU" />
<direct name="REGCLKBL" input="RAMBFIFO36E1.REGCLKBL" output="RAMB36E1.REGCLKBL" />
<direct name="RSTRAMBU" input="RAMBFIFO36E1.RSTRAMBU" output="RAMB36E1.RSTRAMBU" />
<direct name="RSTRAMBL" input="RAMBFIFO36E1.RSTRAMBL" output="RAMB36E1.RSTRAMBL" />
<direct name="RSTREGBU" input="RAMBFIFO36E1.RSTREGBU" output="RAMB36E1.RSTREGBU" />
<direct name="RSTREGBL" input="RAMBFIFO36E1.RSTREGBL" output="RAMB36E1.RSTREGBL" />
<direct name="ADDRBWRADDRU" input="RAMBFIFO36E1.ADDRBWRADDRU" output="RAMB36E1.ADDRBWRADDRU" />
<direct name="ADDRBWRADDRL" input="RAMBFIFO36E1.ADDRBWRADDRL" output="RAMB36E1.ADDRBWRADDRL" />
<direct name="DIBDI" input="RAMBFIFO36E1.DIBDI" output="RAMB36E1.DIBDI" />
<direct name="DIPBDIP" input="RAMBFIFO36E1.DIPBDIP" output="RAMB36E1.DIPBDIP" />
<direct name="WEBWEU" input="RAMBFIFO36E1.WEBWEU" output="RAMB36E1.WEBWEU" />
<direct name="WEBWEL" input="RAMBFIFO36E1.WEBWEL" output="RAMB36E1.WEBWEL" />
<!-- Port B outputs -->
<direct name="DOBDO" input="RAMB36E1.DOBDO" output="RAMBFIFO36E1.DOBDO" />
<direct name="DOPBDOP" input="RAMB36E1.DOPBDOP" output="RAMBFIFO36E1.DOPBDOP" />
<!-- Other pins -->
<direct name="CASCADEINA" input="RAMBFIFO36E1.CASCADEINA" output="RAMB36E1.CASCADEINA" />
<direct name="CASCADEINB" input="RAMBFIFO36E1.CASCADEINB" output="RAMB36E1.CASCADEINB" />
<direct name="CASCADEOUTA" input="RAMB36E1.CASCADEOUTA" output="RAMBFIFO36E1.CASCADEOUTA" />
<direct name="CASCADEOUTB" input="RAMB36E1.CASCADEOUTB" output="RAMBFIFO36E1.CASCADEOUTB" />
</interconnect>
</mode>
</pb_type>
Model XML¶
<!-- vim: set ai sw=1 ts=1 sta et: -->
<models>
<model name="RAMB36E1_PRIM">
<input_ports>
<!-- Port A - 32bit wide -->
<port is_clock="1" name="CLKARDCLKU" />
<port is_clock="1" name="CLKARDCLKL" />
<port clock="CLKARDCLKL" name="ENARDENU" />
<port clock="CLKARDCLKL" name="ENARDENL" />
<port clock="CLKARDCLKL" name="REGCEAREGCEU" />
<port clock="CLKARDCLKL" name="REGCEAREGCEL" />
<port clock="CLKARDCLKL" name="REGCLKARDRCLKU" />
<port clock="CLKARDCLKL" name="REGCLKARDRCLKL" />
<port clock="CLKARDCLKL" name="RSTRAMARSTRAMU" />
<port clock="CLKARDCLKL" name="RSTRAMARSTRAMLRST" />
<port clock="CLKARDCLKL" name="RSTREGARSTREGU" />
<port clock="CLKARDCLKL" name="RSTREGARSTREGL" />
<port clock="CLKARDCLKL" name="ADDRARDADDRU" />
<port clock="CLKARDCLKL" name="ADDRARDADDRL" />
<port clock="CLKARDCLKL" name="DIADI" />
<port clock="CLKARDCLKL" name="DIPADIP" />
<port clock="CLKARDCLKL" name="WEAU" />
<port clock="CLKARDCLKL" name="WEAL" />
<!-- Port B - 32bit wide -->
<port is_clock="1" name="CLKBWRCLKU" />
<port is_clock="1" name="CLKBWRCLKL" />
<port clock="CLKBWRCLKL" name="ENBWRENU" />
<port clock="CLKBWRCLKL" name="ENBWRENL" />
<port clock="CLKBWRCLKL" name="REGCEBU" />
<port clock="CLKBWRCLKL" name="REGCEBL" />
<port clock="CLKBWRCLKL" name="REGCLKBU" />
<port clock="CLKBWRCLKL" name="REGCLKBL" />
<port clock="CLKBWRCLKL" name="RSTRAMBU" />
<port clock="CLKBWRCLKL" name="RSTRAMBL" />
<port clock="CLKBWRCLKL" name="RSTREGBU" />
<port clock="CLKBWRCLKL" name="RSTREGBL" />
<port clock="CLKBWRCLKL" name="ADDRBWRADDRU" />
<port clock="CLKBWRCLKL" name="ADDRBWRADDRL" />
<port clock="CLKBWRCLKL" name="DIBDI" />
<port clock="CLKBWRCLKL" name="DIPBDIP" />
<port clock="CLKBWRCLKL" name="WEBWEU" />
<port clock="CLKBWRCLKL" name="WEBWEL" />
<!-- FIXME -->
<port name="CASCADEINA" />
<port name="CASCADEINB" />
</input_ports>
<output_ports>
<!-- Port A - 32bit wide -->
<port clock="CLKARDCLKL" name="DOADO" />
<port clock="CLKARDCLKL" name="DOPADOP" />
<!-- Port B - 32bit wide -->
<port clock="CLKBWRCLKL" name="DOBDO" />
<port clock="CLKBWRCLKL" name="DOPBDOP" />
<!-- FIXME -->
<port name="CASCADEOUTA" />
<port name="CASCADEOUTB" />
</output_ports>
</model>
</models>