symbiflow-arch-defs

Table Of Contents

LUT2

Component Diagram

Internal Diagram

Verilog File

`default_nettype none
module LUT2(input A, B, output Z);
    parameter [3:0] INIT = 4'h0;
    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
    assign Z =      A ?          s1[1] :         s1[0];
endmodule

Table Of Contents

• LUT2
  • Component Diagram
  • Internal Diagram
  • Verilog File

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