carry0¶

Component Diagram¶

Internal Diagram¶

/home/docs/checkouts/readthedocs.org/user_builds/rw1nkler-symbiflow-arch-defs/checkouts/latest/xc/common/primitives/common_slice/carry/carry0.sim.v

Verilog File¶

(* whitebox *)
module CARRY0_CONST(O, CO_CHAIN, CO_FABRIC, CI_INIT, CI, DI, S);
  (* DELAY_CONST_CI="10e-12" *)
  (* DELAY_CONST_CI_INIT="10e-12" *)
  (* DELAY_CONST_S="10e-12" *)
  output wire O;

  (* DELAY_CONST_CI="10e-12" *)
  (* DELAY_CONST_CI_INIT="10e-12" *)
  (* DELAY_CONST_DI="10e-12" *)
  (* DELAY_CONST_S="10e-12" *)
  output wire CO_CHAIN, CO_FABRIC;
  input wire CI_INIT, CI, DI, S;

  assign CI_COMBINE = CI | CI_INIT;
  assign CO_CHAIN = S ? CI_COMBINE : DI;
  assign CO_FABRIC = CO_CHAIN;
  assign O = CI_COMBINE ^ S;
endmodule

Physical Block XML¶

<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt CARRY0_CONST" name="CARRY0" num_pb="1">
  <input  name="CI"        num_pins="1"/>
  <input  name="CI_INIT"   num_pins="1"/>
  <output name="CO_CHAIN"  num_pins="1"/>
  <output name="CO_FABRIC" num_pins="1"/>
  <input  name="DI"        num_pins="1"/>
  <output name="O"         num_pins="1"/>
  <input  name="S"         num_pins="1"/>
  <delay_constant in_port="CI"      max="10e-12" out_port="CO_CHAIN"/>
  <delay_constant in_port="CI_INIT" max="10e-12" out_port="CO_CHAIN"/>
  <delay_constant in_port="DI"      max="10e-12" out_port="CO_CHAIN"/>
  <delay_constant in_port="S"       max="10e-12" out_port="CO_CHAIN"/>
  <delay_constant in_port="CI"      max="10e-12" out_port="CO_FABRIC"/>
  <delay_constant in_port="CI_INIT" max="10e-12" out_port="CO_FABRIC"/>
  <delay_constant in_port="DI"      max="10e-12" out_port="CO_FABRIC"/>
  <delay_constant in_port="S"       max="10e-12" out_port="CO_FABRIC"/>
  <delay_constant in_port="CI"      max="10e-12" out_port="O"/>
  <delay_constant in_port="CI_INIT" max="10e-12" out_port="O"/>
  <delay_constant in_port="S"       max="10e-12" out_port="O"/>
  <metadata>
    <meta name="fasm_params">
      PRECYINIT.C0 = CYINIT_C0
      PRECYINIT.C1 = CYINIT_C1
    </meta>
    <meta name="type">bel</meta>
    <meta name="subtype">blackbox</meta>
  </metadata>
</pb_type>

Model XML¶

<models xmlns:xi="http://www.w3.org/2001/XInclude">
  <model name="CARRY0_CONST">
    <input_ports>
      <port combinational_sink_ports="CO_CHAIN CO_FABRIC O" name="CI"/>
      <port combinational_sink_ports="CO_CHAIN CO_FABRIC O" name="CI_INIT"/>
      <port combinational_sink_ports="CO_CHAIN CO_FABRIC" name="DI"/>
      <port combinational_sink_ports="CO_CHAIN CO_FABRIC O" name="S"/>
    </input_ports>
    <output_ports>
      <port name="CO_CHAIN"/>
      <port name="CO_FABRIC"/>
      <port name="O"/>
    </output_ports>
  </model>
</models>