sb_lut¶

Physical Block XML¶

<!-- set: ai sw=1 ts=1 sta et -->
<!-- 4 input LUT found in the ICE40 -->
<pb_type name="LUT" num_pb="1">
 <input  name="in" num_pins="4" />
 <output name="out" num_pins="1" />
 <!--
    FIXME: The VPR LUT mode must be first, otherwise VPR can't route
    through the LUT.
 -->
 <mode name="VPR_LUT4">
  <pb_type name="LUT4" num_pb="1" class="lut" blif_model=".names">
   <input  name="in"  num_pins="4" port_class="lut_in" />
   <output name="out" num_pins="1" port_class="lut_out" />
   <metadata>
    <meta name="type">block</meta>
    <meta name="subtype">ignore</meta>
   </metadata>
  </pb_type>
  <interconnect>
   <direct><port type="input" name="in"/><port type="output" from="LUT4" name="in"/></direct>
   <direct><port type="input" from="LUT4" name="out"/><port type="output" name="out"/>
    <pack_pattern name="LUT+FFA"/>
    <pack_pattern name="LUT+FFB"/>
    <pack_pattern name="LUT+FFC"/>
    <pack_pattern name="LUT+FFD"/>
    <pack_pattern name="LUT+FFE"/>
    <pack_pattern name="LUT+FFF"/>
    <pack_pattern name="LUT+FFG"/>
    <pack_pattern name="LUT+FFH"/>
    <pack_pattern name="LUT+FFI"/>
    <pack_pattern name="LUT+FFJ"/>
    <pack_pattern name="LUT+FFK"/>
    <pack_pattern name="LUT+FFL"/>
    <pack_pattern name="LUT+FFM"/>
    <pack_pattern name="LUT+FFN"/>
    <pack_pattern name="LUT+FFO"/>
    <pack_pattern name="LUT+FFP"/>
    <pack_pattern name="LUT+FFQ"/>
    <pack_pattern name="LUT+FFR"/>
    <pack_pattern name="LUT+FFS"/>
    <pack_pattern name="LUT+FFT"/>
    <pack_pattern name="LUT+FFU"/>
   </direct>
  </interconnect>
 </mode>
 <mode name="SB_LUT4">
  <pb_type name="SB_LUT4" num_pb="1" blif_model=".subckt SB_LUT4">
   <input  name="I0" num_pins="1" />
   <input  name="I1" num_pins="1" />
   <input  name="I2" num_pins="1" />
   <input  name="I3" num_pins="1" />
   <output name="O"  num_pins="1" />
   <metadata>
    <meta name="type">block</meta>
    <meta name="subtype">ignore</meta>
   </metadata>
  </pb_type>
  <interconnect>
   <direct><port type="input" name="in[0]"/><port type="output" from="SB_LUT4" name="I0"/></direct>
   <direct><port type="input" name="in[1]"/><port type="output" from="SB_LUT4" name="I1"/></direct>
   <direct><port type="input" name="in[2]"/><port type="output" from="SB_LUT4" name="I2"/></direct>
   <direct><port type="input" name="in[3]"/><port type="output" from="SB_LUT4" name="I3"/></direct>
   <direct><port type="input" from="SB_LUT4" name="O"/><port type="output" name="out"/>
   </direct>
  </interconnect>
 </mode>
 <metadata>
  <meta name="type">bel</meta>
  <meta name="subtype">lut</meta>
 </metadata>
</pb_type>

Model XML¶

<!-- set: ai sw=1 ts=1 sta et -->
 <models>
  <model name="SB_LUT4">
   <input_ports>
    <port name="I0" combinational_sink_ports="O" />
    <port name="I1" combinational_sink_ports="O" />
    <port name="I2" combinational_sink_ports="O" />
    <port name="I3" combinational_sink_ports="O" />
   </input_ports>
   <output_ports>
    <port name="O" />
   </output_ports>
  </model>
 </models>