symbiflow-arch-defs
symbiflow-arch-defs

d_dram

Physical Block XML

<pb_type name="D_DRAM" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
  <clock  name="CLK" num_pins="1" />
  <input  name="A"   num_pins="6" />
  <input  name="WA7" num_pins="1" />
  <input  name="WA8" num_pins="1" />
  <input  name="DI1" num_pins="1" />
  <input  name="DI2" num_pins="1" />
  <input  name="WE"  num_pins="1" />

  <output name="SO6"  num_pins="1" />
  <output name="SO6_32"  num_pins="1" />
  <output name="SO5_32"  num_pins="1" />
  <output name="O6"  num_pins="1" />
  <output name="O5"  num_pins="1" />

 <!-- TODO: Missing modes: SRL. -->
 <mode name="NO_DRAM">
  <pb_type name="BEL_NULL-NO_DRAM" num_pb="1" blif_model=".subckt NO_DRAM">
    <input  name="A" num_pins="6"/>
  </pb_type>
  <interconnect>
    <direct name="A" input="D_DRAM.A" output="BEL_NULL-NO_DRAM.A" />
  </interconnect>
 </mode>
 <mode name="64_SINGLE_PORT">
   <xi:include href="dpram64.pb_type.xml" />
   <interconnect>
     <direct name="CLK" input="D_DRAM.CLK" output="DPRAM64.CLK" />
     <direct name="A" input="D_DRAM.A" output="DPRAM64.A" />
     <direct name="WA" input="D_DRAM.A" output="DPRAM64.WA" />
     <direct name="WA7" input="D_DRAM.WA7" output="DPRAM64.WA7" />
     <direct name="WA8" input="D_DRAM.WA8" output="DPRAM64.WA8" />
     <direct name="DI" input="D_DRAM.DI1" output="DPRAM64.DI" />
     <direct name="WE" input="D_DRAM.WE" output="DPRAM64.WE" />

     <direct name="O6" input="DPRAM64.O" output="D_DRAM.O6" />
     <direct name="SO6" input="DPRAM64.O" output="D_DRAM.SO6" />
   </interconnect>
 </mode>
 <mode name="32_DUAL_PORT">
   <pb_type name="DPRAM32_O6" num_pb="1" blif_model=".subckt DPRAM32">
    <xi:include href="dpram32.pb_type.xml" xpointer="xpointer(pb_type/child::node()[local-name()!='metadata'])" />
    <metadata>
     <xi:include href="dpram32.pb_type.xml" xpointer="xpointer(pb_type/metadata/child::node())" />
     <meta name="fasm_params">
      INIT[63:32] = INIT_00
     </meta>
    </metadata>
   </pb_type>
   <pb_type name="DPRAM32_O5" num_pb="1" blif_model=".subckt DPRAM32">
    <xi:include href="dpram32.pb_type.xml" xpointer="xpointer(pb_type/child::node()[local-name()!='metadata'])" />
    <metadata>
     <xi:include href="dpram32.pb_type.xml" xpointer="xpointer(pb_type/metadata/child::node())" />
     <meta name="fasm_params">
      INIT[31:0] = INIT_00
     </meta>
    </metadata>
   </pb_type>
   <interconnect>
     <!-- upper -->
     <direct name="CLK_U" input="D_DRAM.CLK" output="DPRAM32_O6.CLK" />
     <direct name="A_U" input="D_DRAM.A[4:0]" output="DPRAM32_O6.A[4:0]" />
     <direct name="WA_U" input="D_DRAM.A[4:0]" output="DPRAM32_O6.WA[4:0]" />
     <direct name="DI2" input="D_DRAM.DI2" output="DPRAM32_O6.DI" />
     <direct name="WE_U" input="D_DRAM.WE" output="DPRAM32_O6.WE" />

     <direct name="O6" input="DPRAM32_O6.O" output="D_DRAM.O6" />
     <direct name="SO6" input="DPRAM32_O6.O" output="D_DRAM.SO6_32" >
      <pack_pattern  out_port="D_DRAM.SO6_32" name="DRAM_8O_32" in_port="DPRAM32_O6.O" />
      <pack_pattern  out_port="D_DRAM.SO6_32" name="DRAM_DP_32_HI" in_port="DPRAM32_O6.O" />
     </direct>

     <!-- lower -->
     <direct name="CLK_L" input="D_DRAM.CLK" output="DPRAM32_O5.CLK" />
     <direct name="A_L" input="D_DRAM.A[4:0]" output="DPRAM32_O5.A[4:0]" />
     <direct name="WA_L" input="D_DRAM.A[4:0]" output="DPRAM32_O5.WA[4:0]" />
     <direct name="DI" input="D_DRAM.DI1" output="DPRAM32_O5.DI" />
     <direct name="WE_L" input="D_DRAM.WE" output="DPRAM32_O5.WE" />

     <direct name="O5" input="DPRAM32_O5.O" output="D_DRAM.O5" />
     <direct name="SO5" input="DPRAM32_O5.O" output="D_DRAM.SO5_32" >
      <pack_pattern  out_port="D_DRAM.SO5_32" name="DRAM_8O_32" in_port="DPRAM32_O5.O" />
      <pack_pattern  out_port="D_DRAM.SO5_32" name="DRAM_DP_32_HI" in_port="DPRAM32_O5.O" />
     </direct>
   </interconnect>
  </mode>
 <mode name="32_SINGLE_PORT">
   <pb_type name="SPRAM32_O6" num_pb="1" blif_model=".subckt SPRAM32">
    <xi:include href="spram32.pb_type.xml" xpointer="xpointer(pb_type/child::node()[local-name()!='metadata'])" />
    <metadata>
     <xi:include href="spram32.pb_type.xml" xpointer="xpointer(pb_type/metadata/child::node())" />
     <meta name="fasm_params">
      INIT[63:32] = INIT_00
      INIT[31:0] = INIT_ZERO
     </meta>
    </metadata>
   </pb_type>
   <interconnect>
     <direct name="CLK_U" input="D_DRAM.CLK" output="SPRAM32_O6.CLK" />
     <direct name="A_U" input="D_DRAM.A[4:0]" output="SPRAM32_O6.A[4:0]" />
     <direct name="WA_U" input="D_DRAM.A[4:0]" output="SPRAM32_O6.WA[4:0]" />
     <direct name="DI2" input="D_DRAM.DI2" output="SPRAM32_O6.DI" />
     <direct name="WE_U" input="D_DRAM.WE" output="SPRAM32_O6.WE" />

     <direct name="O6" input="SPRAM32_O6.O" output="D_DRAM.O6" />
     <direct name="SO6" input="SPRAM32_O6.O" output="D_DRAM.SO6_32" >
      <pack_pattern out_port="D_DRAM.SO6_32" name="DRAM_QP_32" in_port="SPRAM32_O6.O"/>
    </direct>
   </interconnect>
 </mode>

 <metadata>
  <meta name="fasm_prefix">DLUT</meta>
  <meta name="type">block</meta>
  <meta name="subtype">ignore</meta>
 </metadata>
</pb_type>

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