ramb18e1¶
Physical Block XML¶
<!-- vim: set ai sw=1 ts=1 sta et: -->
<!--
Block RAM in 7 series is 36kbbit split into two 18kbit sections.
The Block RAM is "true dual port".
There are both Latches (first) and Registers (second) on the output (why!?)
The RAM has extra bits that can be used for parity (DIP / DOP).
-->
<pb_type name="RAMB18E1" num_pb="1" blif_model=".subckt RAMB18E1_VPR">
<!-- Port A - 16bit wide -->
<clock name="CLKARDCLK" num_pins="1" />
<input name="REGCEAREGCE" num_pins="1" />
<input name="REGCLKARDRCLK" num_pins="1" />
<input name="ENARDEN" num_pins="1" />
<input name="RSTRAMARSTRAM" num_pins="1" />
<input name="RSTREGARSTREG" num_pins="1" />
<input name="ADDRATIEHIGH" num_pins="2" />
<input name="ADDRARDADDR" num_pins="14" />
<input name="DIADI" num_pins="16" />
<input name="DIPADIP" num_pins="2" />
<input name="WEA" num_pins="4" />
<output name="DOADO" num_pins="16" />
<output name="DOPADOP" num_pins="2" />
<T_setup value="{setup_CLKARDCLKU_ENARDENU}" port="ENARDEN" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_ENARDENU}" port="ENARDEN" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKL_REGCEAL}" port="REGCEAREGCE" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKL_REGCEAL}" port="REGCEAREGCE" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAM" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_RSTRAMAU}" port="RSTRAMARSTRAM" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREG" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_RSTREGAU}" port="RSTREGARSTREG" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_ADDRAU}" port="ADDRARDADDR" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_ADDRAU}" port="ADDRARDADDR" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_DIADIU}" port="DIADI" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_DIADIU}" port="DIADI" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_DIPADIPU}" port="DIPADIP" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_DIPADIPU}" port="DIPADIP" clock="CLKARDCLK" />
<T_setup value="{setup_CLKARDCLKU_WEAU}" port="WEA" clock="CLKARDCLK" />
<T_hold value="{hold_CLKARDCLKU_WEAU}" port="WEA" clock="CLKARDCLK" />
<T_clock_to_Q max="{iopath_CLKARDCLKU_DOADOU}" port="DOADO" clock="CLKARDCLK" />
<T_clock_to_Q max="{iopath_CLKARDCLKU_DOPADOPU}" port="DOPADOP" clock="CLKARDCLK" />
<!-- Fake timing values as there is no database entry for these i/o -->
<T_setup value="10e-12" port="REGCLKARDRCLK" clock="CLKARDCLK" />
<!-- Port B - 16bit wide -->
<clock name="CLKBWRCLK" num_pins="1" />
<input name="ENBWREN" num_pins="1" />
<input name="REGCEB" num_pins="1" />
<input name="REGCLKB" num_pins="1" />
<input name="RSTRAMB" num_pins="1" />
<input name="RSTREGB" num_pins="1" />
<input name="ADDRBTIEHIGH" num_pins="2" />
<input name="ADDRBWRADDR" num_pins="14" />
<input name="DIBDI" num_pins="16" />
<input name="DIPBDIP" num_pins="2" />
<input name="WEBWE" num_pins="8" />
<output name="DOBDO" num_pins="16" />
<output name="DOPBDOP" num_pins="2" />
<T_setup value="{setup_CLKBWRCLKU_ENBWRENU}" port="ENBWREN" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_ENBWRENU}" port="ENBWREN" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_REGCEBU}" port="REGCEB" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_REGCEBU}" port="REGCEB" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMB" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_RSTRAMBU}" port="RSTRAMB" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_RSTREGBU}" port="RSTREGB" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_RSTREGBU}" port="RSTREGB" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_ADDRBU}" port="ADDRBWRADDR" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_ADDRBU}" port="ADDRBWRADDR" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_DIBDIU}" port="DIBDI" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_DIBDIU}" port="DIBDI" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_DIPBDIPU}" port="DIPBDIP" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_DIPBDIPU}" port="DIPBDIP" clock="CLKBWRCLK" />
<T_setup value="{setup_CLKBWRCLKU_WEBU}" port="WEBWE" clock="CLKBWRCLK" />
<T_hold value="{hold_CLKBWRCLKU_WEBU}" port="WEBWE" clock="CLKBWRCLK" />
<T_clock_to_Q max="{iopath_CLKBWRCLKU_DOBDOU}" port="DOBDO" clock="CLKBWRCLK" />
<T_clock_to_Q max="{iopath_CLKBWRCLKU_DOPBDOPU}" port="DOPBDOP" clock="CLKBWRCLK" />
<!-- Fake timing values as there is no database entry for these i/o -->
<T_setup value="10e-12" port="REGCLKB" clock="CLKBWRCLK" />
<metadata>
<meta name="fasm_params">
IN_USE = IN_USE
ZINIT_A[17:0] = ZINIT_A
ZINIT_B[17:0] = ZINIT_B
ZSRVAL_A[17:0] = ZSRVAL_A
ZSRVAL_B[17:0] = ZSRVAL_B
INITP_00[255:0] = INITP_00
INITP_01[255:0] = INITP_01
INITP_02[255:0] = INITP_02
INITP_03[255:0] = INITP_03
INITP_04[255:0] = INITP_04
INITP_05[255:0] = INITP_05
INITP_06[255:0] = INITP_06
INITP_07[255:0] = INITP_07
INIT_00[255:0] = INIT_00
INIT_01[255:0] = INIT_01
INIT_02[255:0] = INIT_02
INIT_03[255:0] = INIT_03
INIT_04[255:0] = INIT_04
INIT_05[255:0] = INIT_05
INIT_06[255:0] = INIT_06
INIT_07[255:0] = INIT_07
INIT_08[255:0] = INIT_08
INIT_09[255:0] = INIT_09
INIT_0A[255:0] = INIT_0A
INIT_0B[255:0] = INIT_0B
INIT_0C[255:0] = INIT_0C
INIT_0D[255:0] = INIT_0D
INIT_0E[255:0] = INIT_0E
INIT_0F[255:0] = INIT_0F
INIT_10[255:0] = INIT_10
INIT_11[255:0] = INIT_11
INIT_12[255:0] = INIT_12
INIT_13[255:0] = INIT_13
INIT_14[255:0] = INIT_14
INIT_15[255:0] = INIT_15
INIT_16[255:0] = INIT_16
INIT_17[255:0] = INIT_17
INIT_18[255:0] = INIT_18
INIT_19[255:0] = INIT_19
INIT_1A[255:0] = INIT_1A
INIT_1B[255:0] = INIT_1B
INIT_1C[255:0] = INIT_1C
INIT_1D[255:0] = INIT_1D
INIT_1E[255:0] = INIT_1E
INIT_1F[255:0] = INIT_1F
INIT_20[255:0] = INIT_20
INIT_21[255:0] = INIT_21
INIT_22[255:0] = INIT_22
INIT_23[255:0] = INIT_23
INIT_24[255:0] = INIT_24
INIT_25[255:0] = INIT_25
INIT_26[255:0] = INIT_26
INIT_27[255:0] = INIT_27
INIT_28[255:0] = INIT_28
INIT_29[255:0] = INIT_29
INIT_2A[255:0] = INIT_2A
INIT_2B[255:0] = INIT_2B
INIT_2C[255:0] = INIT_2C
INIT_2D[255:0] = INIT_2D
INIT_2E[255:0] = INIT_2E
INIT_2F[255:0] = INIT_2F
INIT_30[255:0] = INIT_30
INIT_31[255:0] = INIT_31
INIT_32[255:0] = INIT_32
INIT_33[255:0] = INIT_33
INIT_34[255:0] = INIT_34
INIT_35[255:0] = INIT_35
INIT_36[255:0] = INIT_36
INIT_37[255:0] = INIT_37
INIT_38[255:0] = INIT_38
INIT_39[255:0] = INIT_39
INIT_3A[255:0] = INIT_3A
INIT_3B[255:0] = INIT_3B
INIT_3C[255:0] = INIT_3C
INIT_3D[255:0] = INIT_3D
INIT_3E[255:0] = INIT_3E
INIT_3F[255:0] = INIT_3F
ZINV_CLKARDCLK = ZINV_CLKARDCLK
ZINV_CLKBWRCLK = ZINV_CLKBWRCLK
ZINV_ENARDEN = ZINV_ENARDEN
ZINV_ENBWREN = ZINV_ENBWREN
ZINV_RSTRAMARSTRAM = ZINV_RSTRAMARSTRAM
ZINV_RSTRAMB = ZINV_RSTRAMB
ZINV_RSTREGARSTREG = ZINV_RSTREGARSTREG
ZINV_RSTREGB = ZINV_RSTREGB
ZINV_REGCLKARDRCLK = ZINV_REGCLKARDRCLK
ZINV_REGCLKB = ZINV_REGCLKB
DOA_REG = DOA_REG
DOB_REG = DOB_REG
SDP_READ_WIDTH_36 = SDP_READ_WIDTH_36
READ_WIDTH_A_9 = READ_WIDTH_A_9
READ_WIDTH_A_4 = READ_WIDTH_A_4
READ_WIDTH_A_2 = READ_WIDTH_A_2
READ_WIDTH_B_18 = READ_WIDTH_B_18
READ_WIDTH_B_9 = READ_WIDTH_B_9
READ_WIDTH_B_4 = READ_WIDTH_B_4
READ_WIDTH_B_2 = READ_WIDTH_B_2
READ_WIDTH_B_1 = READ_WIDTH_B_1
SDP_WRITE_WIDTH_36 = SDP_WRITE_WIDTH_36
WRITE_WIDTH_A_18 = WRITE_WIDTH_A_18
WRITE_WIDTH_A_9 = WRITE_WIDTH_A_9
WRITE_WIDTH_A_4 = WRITE_WIDTH_A_4
WRITE_WIDTH_A_2 = WRITE_WIDTH_A_2
WRITE_WIDTH_A_1 = WRITE_WIDTH_A_1
WRITE_WIDTH_B_18 = WRITE_WIDTH_B_18
WRITE_WIDTH_B_9 = WRITE_WIDTH_B_9
WRITE_WIDTH_B_4 = WRITE_WIDTH_B_4
WRITE_WIDTH_B_2 = WRITE_WIDTH_B_2
WRITE_WIDTH_B_1 = WRITE_WIDTH_B_1
WRITE_MODE_A_NO_CHANGE = WRITE_MODE_A_NO_CHANGE
WRITE_MODE_A_READ_FIRST = WRITE_MODE_A_READ_FIRST
WRITE_MODE_B_NO_CHANGE = WRITE_MODE_B_NO_CHANGE
WRITE_MODE_B_READ_FIRST = WRITE_MODE_B_READ_FIRST
</meta>
<meta name="type">bel</meta>
<meta name="subtype">memory</meta>
</metadata>
</pb_type>
Model XML¶
<!-- vim: set ai sw=1 ts=1 sta et: -->
<models>
<model name="RAMB18E1_VPR">
<input_ports>
<!-- Port A - 16bit wide -->
<port is_clock="1" name="CLKARDCLK" />
<port clock="CLKARDCLK" name="ENARDEN" />
<port clock="CLKARDCLK" name="REGCEAREGCE" />
<port clock="CLKARDCLK" name="REGCLKARDRCLK" />
<port clock="CLKARDCLK" name="RSTRAMARSTRAM" />
<port clock="CLKARDCLK" name="RSTREGARSTREG" />
<port name="ADDRATIEHIGH" />
<port clock="CLKARDCLK" name="ADDRARDADDR" />
<port clock="CLKARDCLK" name="DIADI" />
<port clock="CLKARDCLK" name="DIPADIP" />
<port clock="CLKARDCLK" name="WEA" />
<!-- Port B - 16bit wide -->
<port is_clock="1" name="CLKBWRCLK" />
<port clock="CLKBWRCLK" name="ENBWREN" />
<port clock="CLKBWRCLK" name="REGCLKB" />
<port clock="CLKBWRCLK" name="REGCEB" />
<port clock="CLKBWRCLK" name="RSTRAMB" />
<port clock="CLKBWRCLK" name="RSTREGB" />
<port name="ADDRBTIEHIGH" />
<port clock="CLKBWRCLK" name="ADDRBWRADDR" />
<port clock="CLKBWRCLK" name="DIBDI" />
<port clock="CLKBWRCLK" name="DIPBDIP" />
<port clock="CLKBWRCLK" name="WEBWE" />
</input_ports>
<output_ports>
<!-- Port A - 16bit wide -->
<port clock="CLKARDCLK" name="DOADO" />
<port clock="CLKARDCLK" name="DOPADOP" />
<!-- Port B - 16bit wide -->
<port clock="CLKBWRCLK" name="DOBDO" />
<port clock="CLKBWRCLK" name="DOPBDOP" />
</output_ports>
</model>
</models>