sb_ram¶
Physical Block XML¶
<!-- set: ai sw=1 ts=1 sta et -->
<!-- Block ram found inside the iCE40 -->
<pb_type name="SB_RAM" num_pb="1">
<!-- Read port -->
<output name="RDATA" num_pins="16"/>
<clock name="RCLK" num_pins="1"/>
<input name="RCLKE" num_pins="1"/>
<input name="RE" num_pins="1"/>
<input name="RADDR" num_pins="11"/>
<!-- Write port -->
<clock name="WCLK" num_pins="1"/>
<input name="WCLKE" num_pins="1"/>
<input name="WE" num_pins="1"/>
<input name="WADDR" num_pins="11"/>
<input name="MASK" num_pins="16"/>
<input name="WDATA" num_pins="16"/>
<mode name="SB_RAM40_4K">
<!--
<pb_type name="SB_RAM256x16" blif_model=".subckt dual_port_ram" num_pb="1" class="memory">
<output name="RDATA" num_pins="16" port_class="data_out1" />
<input name="RADDR" num_pins="8" port_class="address1" />
<clock name="CLK1" num_pins="1" port_class="clock1" />
<input name="DATAIN2" num_pins="16" port_class="data_in2" />
<input name="WE2" num_pins="1" port_class="write_en2" />
<input name="WADDR" num_pins="8" port_class="address2" />
<clock name="WCLK" num_pins="1" port_class="clock2" />
-->
<pb_type name="SB_RAM256x16" blif_model=".subckt SB_RAM40_4K" num_pb="1">
<!-- Read port -->
<output name="RDATA" num_pins="16"/>
<clock name="RCLK" num_pins="1"/>
<input name="RCLKE" num_pins="1"/>
<input name="RE" num_pins="1"/>
<input name="RADDR" num_pins="11"/>
<!-- Write port -->
<clock name="WCLK" num_pins="1"/>
<input name="WCLKE" num_pins="1"/>
<input name="WE" num_pins="1"/>
<input name="WADDR" num_pins="11"/>
<input name="MASK" num_pins="16"/>
<input name="WDATA" num_pins="16"/>
<!-- Read port timing -->
<T_setup value="50e-12" port="RDATA" clock="RCLK"/>
<T_clock_to_Q max="200e-12" port="RCLKE" clock="RCLK"/>
<T_clock_to_Q max="200e-12" port="RE" clock="RCLK"/>
<T_clock_to_Q max="200e-12" port="RADDR" clock="RCLK"/>
<delay_constant max="740e-12" in_port="RCLKE" out_port="RDATA"/>
<delay_constant max="740e-12" in_port="RE" out_port="RDATA"/>
<delay_constant max="740e-12" in_port="RADDR" out_port="RDATA"/>
<!-- Write port timing -->
<T_clock_to_Q max="200e-12" port="WCLKE" clock="WCLK"/>
<T_clock_to_Q max="200e-12" port="WE" clock="WCLK"/>
<T_clock_to_Q max="200e-12" port="WADDR" clock="WCLK"/>
<T_clock_to_Q max="200e-12" port="MASK" clock="WCLK"/>
<T_clock_to_Q max="200e-12" port="WDATA" clock="WCLK"/>
<delay_constant max="740e-12" in_port="WCLKE" out_port="SB_RAM256x16.RDATA"/>
<delay_constant max="740e-12" in_port="WE" out_port="SB_RAM256x16.RDATA"/>
<delay_constant max="740e-12" in_port="WADDR" out_port="SB_RAM256x16.RDATA"/>
<delay_constant max="740e-12" in_port="MASK" out_port="SB_RAM256x16.RDATA"/>
<delay_constant max="740e-12" in_port="WDATA" out_port="SB_RAM256x16.RDATA"/>
<metadata>
<meta name="fasm_params">
INIT0[255:0] = INIT_0
INIT1[255:0] = INIT_1
INIT2[255:0] = INIT_2
INIT3[255:0] = INIT_3
INIT4[255:0] = INIT_4
INIT5[255:0] = INIT_5
INIT6[255:0] = INIT_6
INIT7[255:0] = INIT_7
INIT8[255:0] = INIT_8
INIT9[255:0] = INIT_9
INITA[255:0] = INIT_A
INITB[255:0] = INIT_B
INITC[255:0] = INIT_C
INITD[255:0] = INIT_D
INITE[255:0] = INIT_E
INITF[255:0] = INIT_F
WRITE_MODE[1:0] = WRITE_MODE
READ_MODE [1:0] = READ_MODE
</meta>
</metadata>
</pb_type>
<interconnect>
<!-- Read port -->
<direct><port type="input" from="SB_RAM256x16" name="RDATA[0]"/><port type="output" name="RDATA[0]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[1]"/><port type="output" name="RDATA[1]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[2]"/><port type="output" name="RDATA[2]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[3]"/><port type="output" name="RDATA[3]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[4]"/><port type="output" name="RDATA[4]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[5]"/><port type="output" name="RDATA[5]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[6]"/><port type="output" name="RDATA[6]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[7]"/><port type="output" name="RDATA[7]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[8]"/><port type="output" name="RDATA[8]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[9]"/><port type="output" name="RDATA[9]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[10]"/><port type="output" name="RDATA[10]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[11]"/><port type="output" name="RDATA[11]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[12]"/><port type="output" name="RDATA[12]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[13]"/><port type="output" name="RDATA[13]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[14]"/><port type="output" name="RDATA[14]"/></direct>
<direct><port type="input" from="SB_RAM256x16" name="RDATA[15]"/><port type="output" name="RDATA[15]"/></direct>
<direct><port type="input" name="RCLK"/><port type="output" from="SB_RAM256x16" name="RCLK"/></direct>
<direct><port type="input" name="RCLKE"/><port type="output" from="SB_RAM256x16" name="RCLKE"/></direct>
<direct><port type="input" name="RE"/><port type="output" from="SB_RAM256x16" name="RE"/></direct>
<direct><port type="input" name="RADDR[0]"/><port type="output" from="SB_RAM256x16" name="RADDR[0]"/></direct>
<direct><port type="input" name="RADDR[1]"/><port type="output" from="SB_RAM256x16" name="RADDR[1]"/></direct>
<direct><port type="input" name="RADDR[2]"/><port type="output" from="SB_RAM256x16" name="RADDR[2]"/></direct>
<direct><port type="input" name="RADDR[3]"/><port type="output" from="SB_RAM256x16" name="RADDR[3]"/></direct>
<direct><port type="input" name="RADDR[4]"/><port type="output" from="SB_RAM256x16" name="RADDR[4]"/></direct>
<direct><port type="input" name="RADDR[5]"/><port type="output" from="SB_RAM256x16" name="RADDR[5]"/></direct>
<direct><port type="input" name="RADDR[6]"/><port type="output" from="SB_RAM256x16" name="RADDR[6]"/></direct>
<direct><port type="input" name="RADDR[7]"/><port type="output" from="SB_RAM256x16" name="RADDR[7]"/></direct>
<direct><port type="input" name="RADDR[8]"/><port type="output" from="SB_RAM256x16" name="RADDR[8]"/></direct>
<direct><port type="input" name="RADDR[9]"/><port type="output" from="SB_RAM256x16" name="RADDR[9]"/></direct>
<direct><port type="input" name="RADDR[10]"/><port type="output" from="SB_RAM256x16" name="RADDR[10]"/></direct>
<!-- Write port -->
<direct><port type="input" name="WCLK"/><port type="output" from="SB_RAM256x16" name="WCLK"/></direct>
<direct><port type="input" name="WCLKE"/><port type="output" from="SB_RAM256x16" name="WCLKE"/></direct>
<direct><port type="input" name="WE"/><port type="output" from="SB_RAM256x16" name="WE"/></direct>
<direct><port type="input" name="WADDR[0]"/><port type="output" from="SB_RAM256x16" name="WADDR[0]"/></direct>
<direct><port type="input" name="WADDR[1]"/><port type="output" from="SB_RAM256x16" name="WADDR[1]"/></direct>
<direct><port type="input" name="WADDR[2]"/><port type="output" from="SB_RAM256x16" name="WADDR[2]"/></direct>
<direct><port type="input" name="WADDR[3]"/><port type="output" from="SB_RAM256x16" name="WADDR[3]"/></direct>
<direct><port type="input" name="WADDR[4]"/><port type="output" from="SB_RAM256x16" name="WADDR[4]"/></direct>
<direct><port type="input" name="WADDR[5]"/><port type="output" from="SB_RAM256x16" name="WADDR[5]"/></direct>
<direct><port type="input" name="WADDR[6]"/><port type="output" from="SB_RAM256x16" name="WADDR[6]"/></direct>
<direct><port type="input" name="WADDR[7]"/><port type="output" from="SB_RAM256x16" name="WADDR[7]"/></direct>
<direct><port type="input" name="WADDR[8]"/><port type="output" from="SB_RAM256x16" name="WADDR[8]"/></direct>
<direct><port type="input" name="WADDR[9]"/><port type="output" from="SB_RAM256x16" name="WADDR[9]"/></direct>
<direct><port type="input" name="WADDR[10]"/><port type="output" from="SB_RAM256x16" name="WADDR[10]"/></direct>
<direct><port type="input" name="MASK[0]"/><port type="output" from="SB_RAM256x16" name="MASK[0]"/></direct>
<direct><port type="input" name="MASK[1]"/><port type="output" from="SB_RAM256x16" name="MASK[1]"/></direct>
<direct><port type="input" name="MASK[2]"/><port type="output" from="SB_RAM256x16" name="MASK[2]"/></direct>
<direct><port type="input" name="MASK[3]"/><port type="output" from="SB_RAM256x16" name="MASK[3]"/></direct>
<direct><port type="input" name="MASK[4]"/><port type="output" from="SB_RAM256x16" name="MASK[4]"/></direct>
<direct><port type="input" name="MASK[5]"/><port type="output" from="SB_RAM256x16" name="MASK[5]"/></direct>
<direct><port type="input" name="MASK[6]"/><port type="output" from="SB_RAM256x16" name="MASK[6]"/></direct>
<direct><port type="input" name="MASK[7]"/><port type="output" from="SB_RAM256x16" name="MASK[7]"/></direct>
<direct><port type="input" name="MASK[8]"/><port type="output" from="SB_RAM256x16" name="MASK[8]"/></direct>
<direct><port type="input" name="MASK[9]"/><port type="output" from="SB_RAM256x16" name="MASK[9]"/></direct>
<direct><port type="input" name="MASK[10]"/><port type="output" from="SB_RAM256x16" name="MASK[10]"/></direct>
<direct><port type="input" name="MASK[11]"/><port type="output" from="SB_RAM256x16" name="MASK[11]"/></direct>
<direct><port type="input" name="MASK[12]"/><port type="output" from="SB_RAM256x16" name="MASK[12]"/></direct>
<direct><port type="input" name="MASK[13]"/><port type="output" from="SB_RAM256x16" name="MASK[13]"/></direct>
<direct><port type="input" name="MASK[14]"/><port type="output" from="SB_RAM256x16" name="MASK[14]"/></direct>
<direct><port type="input" name="MASK[15]"/><port type="output" from="SB_RAM256x16" name="MASK[15]"/></direct>
<direct><port type="input" name="WDATA[0]"/><port type="output" from="SB_RAM256x16" name="WDATA[0]"/></direct>
<direct><port type="input" name="WDATA[1]"/><port type="output" from="SB_RAM256x16" name="WDATA[1]"/></direct>
<direct><port type="input" name="WDATA[2]"/><port type="output" from="SB_RAM256x16" name="WDATA[2]"/></direct>
<direct><port type="input" name="WDATA[3]"/><port type="output" from="SB_RAM256x16" name="WDATA[3]"/></direct>
<direct><port type="input" name="WDATA[4]"/><port type="output" from="SB_RAM256x16" name="WDATA[4]"/></direct>
<direct><port type="input" name="WDATA[5]"/><port type="output" from="SB_RAM256x16" name="WDATA[5]"/></direct>
<direct><port type="input" name="WDATA[6]"/><port type="output" from="SB_RAM256x16" name="WDATA[6]"/></direct>
<direct><port type="input" name="WDATA[7]"/><port type="output" from="SB_RAM256x16" name="WDATA[7]"/></direct>
<direct><port type="input" name="WDATA[8]"/><port type="output" from="SB_RAM256x16" name="WDATA[8]"/></direct>
<direct><port type="input" name="WDATA[9]"/><port type="output" from="SB_RAM256x16" name="WDATA[9]"/></direct>
<direct><port type="input" name="WDATA[10]"/><port type="output" from="SB_RAM256x16" name="WDATA[10]"/></direct>
<direct><port type="input" name="WDATA[11]"/><port type="output" from="SB_RAM256x16" name="WDATA[11]"/></direct>
<direct><port type="input" name="WDATA[12]"/><port type="output" from="SB_RAM256x16" name="WDATA[12]"/></direct>
<direct><port type="input" name="WDATA[13]"/><port type="output" from="SB_RAM256x16" name="WDATA[13]"/></direct>
<direct><port type="input" name="WDATA[14]"/><port type="output" from="SB_RAM256x16" name="WDATA[14]"/></direct>
<direct><port type="input" name="WDATA[15]"/><port type="output" from="SB_RAM256x16" name="WDATA[15]"/></direct>
</interconnect>
</mode>
<metadata>
<meta name="fasm_features">
RamConfig.PowerUp
</meta>
</metadata>
</pb_type>
Model XML¶
<!-- set: ai sw=1 ts=1 sta et -->
<models>
<model name="SB_RAM40_4K">
<input_ports>
<!-- Read port -->
<port name="RCLK" is_clock="1"/>
<port name="RCLKE" clock="RCLK" combinational_sink_ports="RDATA"/>
<port name="RE" clock="RCLK" combinational_sink_ports="RDATA"/>
<port name="RADDR" clock="RCLK" combinational_sink_ports="RDATA"/>
<!-- Write port -->
<port name="WCLK" is_clock="1"/>
<port name="WCLKE" clock="WCLK" combinational_sink_ports="RDATA"/>
<port name="WE" clock="WCLK" combinational_sink_ports="RDATA"/>
<port name="WADDR" clock="WCLK" combinational_sink_ports="RDATA"/>
<port name="MASK" clock="WCLK" combinational_sink_ports="RDATA"/>
<port name="WDATA" clock="WCLK" combinational_sink_ports="RDATA"/>
</input_ports>
<output_ports>
<port name="RDATA" clock="RCLK"/>
</output_ports>
</model>
</models>