symbiflow-arch-defs
symbiflow-arch-defs

common_slice

Component Diagram

`include "Nlut/alut.sim.v" `include "Nlut/blut.sim.v" `include "Nlut/clut.sim.v" `include "Nlut/dlut.sim.v" `include "muxes/f7amux/f7amux.sim.v" `include "muxes/f7bmux/f7bmux.sim.v" `include "muxes/f8mux/f8mux.sim.v" `include "routing/affmux/affmux.sim.v" `include "routing/bffmux/bffmux.sim.v" `include "routing/cffmux/cffmux.sim.v" `include "routing/dffmux/dffmux.sim.v" `include "routing/aoutmux/aoutmux.sim.v" `include "routing/boutmux/boutmux.sim.v" `include "routing/coutmux/coutmux.sim.v" `include "routing/doutmux/doutmux.sim.v" `include "routing/precyinit_mux/precyinit_mux.sim.v" `include "routing/coutused/coutused.sim.v" `include "routing/srusedmux/srusedmux.sim.v" `include "routing/ceusedmux/ceusedmux.sim.v" `include "routing/N5ffmux/a5ffmux.sim.v" `include "routing/N5ffmux/b5ffmux.sim.v" `include "routing/N5ffmux/c5ffmux.sim.v" `include "routing/N5ffmux/d5ffmux.sim.v" `include "routing/Ncy0/acy0.sim.v" `include "routing/Ncy0/bcy0.sim.v" `include "routing/Ncy0/ccy0.sim.v" `include "routing/Ncy0/dcy0.sim.v" `include "routing/Nused/aused.sim.v" `include "routing/Nused/bused.sim.v" `include "routing/Nused/cused.sim.v" `include "routing/Nused/dused.sim.v" `include "carry/carry4_vpr.sim.v" `include "routing/clkinv/clkinv.sim.v" // Broken module COMMON_SLICE( DX, D1, D2, D3, D4, D5, D6, DMUX, D, DQ, // D port CX, C1, C2, C3, C4, C5, C6, CMUX, C, CQ, // C port BX, B1, B2, B3, B4, B5, B6, BMUX, B, BQ, // B port AX, A1, A2, A3, A4, A5, A6, AMUX, A, AQ, // A port SR, CE, CLK, // Flip flop signals CIN, CYINIT, COUT, // Carry to/from adjacent slices ); // D port input wire DX; input wire D1; input wire D2; input wire D3; input wire D4; input wire D5; input wire D6; output wire DMUX; output wire D; output wire DQ; // D port flip-flop config parameter D5FF_SRVAL = "SRLOW"; parameter D5FF_INIT = D5FF_SRVAL; parameter DFF_SRVAL = "SRLOW"; parameter DFF_INIT = D5FF_SRVAL; // C port input wire CX; input wire C1; input wire C2; input wire C3; input wire C4; input wire C5; input wire C6; output wire CMUX; output wire C; output wire CQ; // B port input wire BX; input wire B1; input wire B2; input wire B3; input wire B4; input wire B5; input wire B6; output wire BMUX; output wire B; output wire BQ; // A port input wire AX; input wire A1; input wire A2; input wire A3; input wire A4; input wire A5; input wire A6; output wire AMUX; output wire A; output wire AQ; // Shared Flip flop signals input wire CLK; // Clock input wire SR; // Set/Reset input wire CE; // Clock enable // Reset type for all flip flops, can be; // * None -- Ignore SR // * Sync -- Reset occurs on clock edge // * Async -- Reset occurs when ever parameter SR_TYPE = "SYNC"; // The mode this unit operates in, can be; // "FLIPFLOP" - Operate as a flip-flop (D->Q on clock low->high) // "LATCH" - Operate as a latch (D->Q while CLK low) parameter FF_MODE = "FLIPFLOP"; // Carry to/from adjacent slices input wire CIN; input wire CYINIT; output wire COUT; // Internal routing configuration wire A5LUT_O5; wire B5LUT_O5; wire C5LUT_O5; wire D5LUT_O5; wire D6LUT_O6; wire C6LUT_O6; wire B6LUT_O6; wire A6LUT_O6; ALUT alut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .O6(A6LUT_O6), .O5(A5LUT_O5)); BLUT blut (.A1(B1), .A2(B2), .A3(B3), .A4(B4), .A5(B5), .A6(B6), .O6(B6LUT_O6), .O5(B5LUT_O5)); CLUT clut (.A1(C1), .A2(C2), .A3(C3), .A4(C4), .A5(C5), .A6(C6), .O6(C6LUT_O6), .O5(C5LUT_O5)); DLUT dlut (.A1(D1), .A2(D2), .A3(D3), .A4(D4), .A5(D5), .A6(D6), .O6(D6LUT_O6), .O5(D5LUT_O5)); wire F7AMUX_OUT; wire F8MUX_OUT; wire A5FFMUX_OUT; wire B5FFMUX_OUT; wire C5FFMUX_OUT; wire D5FFMUX_OUT; A5FFMUX a5ffmux (.IN_B(AX), .IN_A(A5LUT_O5), .O(A5FFMUX_OUT)); B5FFMUX b5ffmux (.IN_B(BX), .IN_A(B5LUT_O5), .O(B5FFMUX_OUT)); C5FFMUX c5ffmux (.IN_B(CX), .IN_A(C5LUT_O5), .O(C5FFMUX_OUT)); D5FFMUX d5ffmux (.IN_B(DX), .IN_A(D5LUT_O5), .O(D5FFMUX_OUT)); wire ACY0_OUT; wire BCY0_OUT; wire CCY0_OUT; wire DCY0_OUT; ACY0 acy0 (.O5(A5LUT_O5), .AX(AX), .O(ACY0_OUT)); BCY0 bcy0 (.O5(B5LUT_O5), .BX(BX), .O(BCY0_OUT)); CCY0 ccy0 (.O5(C5LUT_O5), .CX(CX), .O(CCY0_OUT)); DCY0 dcy0 (.O5(D5LUT_O5), .DX(DX), .O(DCY0_OUT)); wire F7BMUX_OUT; F7BMUX f7bmux (.I0(D6LUT_O6), .I1(C6LUT_O6), .OUT(F7BMUX_OUT), .S0(CX)); wire F7AMUX_OUT; F7BMUX f7amux (.I0(B6LUT_O6), .I1(A6LUT_O6), .OUT(F7AMUX_OUT), .S0(AX)); wire F8MUX_OUT; F8MUX f8mux (.I0(F7BMUX_OUT), .I1(F7AMUX_OUT), .OUT(F8MUX_OUT), .S0(BX)); wire PRECYINIT_OUT; PRECYINIT_MUX precyinit_mux (.C0(0), .C1(1), .CI(CIN), .CYINIT(CYINIT), .OUT(PRECYINIT_OUT)); wire [3:0] CARRY4_CO; wire [3:0] CARRY4_O; CARRY4_MODES carry4 ( .CO(CARRY4_CO), .O(CARRY4_O), .DI({ACY0_OUT, BCY0_OUT, CCY0_OUT, DCY0_OUT}), .S({A6LUT_O6, B6LUT_O6, C6LUT_O6, D6LUT_O6}), .CIN(PRECYINIT_OUT)); COUTUSED coutused (.IN(CARRY4_O[3]), .OUT(COUT)); wire A5FF_Q; wire B5FF_Q; wire C5FF_Q; wire D5FF_Q; AOUTMUX aoutmux ( .A5Q(A5FF_Q), .XOR(CARRY4_O[0]), .O6(A6LUT_O6), .O5(A5LUT_O5), .CY(CARRY4_CO[0]), .F7(F7AMUX_OUT), .OUT(AMUX)); BOUTMUX boutmux ( .B5Q(B5FF_Q), .XOR(CARRY4_O[1]), .O6(B6LUT_O6), .O5(B5LUT_O5), .CY(CARRY4_CO[1]), .F8(F8MUX_OUT), .OUT(BMUX)); COUTMUX coutmux ( .C5Q(C5FF_Q), .XOR(CARRY4_O[2]), .O6(C6LUT_O6), .O5(C5LUT_O5), .CY(CARRY4_CO[2]), .F7(F7BMUX_OUT), .OUT(CMUX)); DOUTMUX doutmux ( .D5Q(D5FF_Q), .XOR(CARRY4_O[3]), .O6(D6LUT_O6), .O5(D5LUT_O5), .CY(CARRY4_CO[3]), .OUT(DMUX)); wire AFFMUX_OUT; wire BFFMUX_OUT; wire CFFMUX_OUT; wire DFFMUX_OUT; AFFMUX affmux ( .AX(AX), .XOR(CARRY4_O[0]), .O6(A6LUT_O6), .O5(A5LUT_O5), .CY(CARRY4_CO[0]), .F7(F7AMUX_OUT), .OUT(AFFMUX_OUT)); BFFMUX bffmux ( .BX(BX), .XOR(CARRY4_O[1]), .O6(B6LUT_O6), .O5(B5LUT_O5), .CY(CARRY4_CO[1]), .F8(F8MUX_OUT), .OUT(BFFMUX_OUT)); CFFMUX cffmux ( .CX(CX), .XOR(CARRY4_O[2]), .O6(C6LUT_O6), .O5(C5LUT_O5), .CY(CARRY4_CO[2]), .F7(F7BMUX_OUT), .OUT(CFFMUX_OUT)); DFFMUX dffmux ( .DX(DX), .XOR(CARRY4_O[3]), .O6(D6LUT_O6), .O5(D5LUT_O5), .CY(CARRY4_CO[3]), .OUT(DFFMUX_OUT)); wire CEUSEDMUX_OUT; wire SRUSEDMUX_OUT; wire CLKINV_OUT; CLKINV clkinv (.CLK(CLK), .OUT(CLKINV_OUT)); A5FF a5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(A5FFMUX_OUT), .Q(A5FF_Q)); B5FF b5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(B5FFMUX_OUT), .Q(B5FF_Q)); C5FF c5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(C5FFMUX_OUT), .Q(C5FF_Q)); D5FF d5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(D5FFMUX_OUT), .Q(D5FF_Q)); A5FF aff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(AFFMUX_OUT), .Q(AQ)); B5FF bff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(BFFMUX_OUT), .Q(BQ)); C5FF cff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(CFFMUX_OUT), .Q(CQ)); D5FF dff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(DFFMUX_OUT), .Q(DQ)); AUSED aused (.I0(A6LUT_O6), .O(A)); BUSED bused (.I0(B6LUT_O6), .O(B)); CUSED cused (.I0(C6LUT_O6), .O(C)); DUSED dused (.I0(D6LUT_O6), .O(D)); CEUSEDMUX ceusedmux (.IN(CE), .OUT(CEUSEDMUX_OUT)); SRUSEDMUX srusedmux (.IN(SR), .OUT(SRUSEDMUX_OUT)); endmodule

Verilog File

`include "Nlut/alut.sim.v"
`include "Nlut/blut.sim.v"
`include "Nlut/clut.sim.v"
`include "Nlut/dlut.sim.v"
`include "muxes/f7amux/f7amux.sim.v"
`include "muxes/f7bmux/f7bmux.sim.v"
`include "muxes/f8mux/f8mux.sim.v"

`include "routing/affmux/affmux.sim.v"
`include "routing/bffmux/bffmux.sim.v"
`include "routing/cffmux/cffmux.sim.v"
`include "routing/dffmux/dffmux.sim.v"

`include "routing/aoutmux/aoutmux.sim.v"
`include "routing/boutmux/boutmux.sim.v"
`include "routing/coutmux/coutmux.sim.v"
`include "routing/doutmux/doutmux.sim.v"

`include "routing/precyinit_mux/precyinit_mux.sim.v"
`include "routing/coutused/coutused.sim.v"

`include "routing/srusedmux/srusedmux.sim.v"
`include "routing/ceusedmux/ceusedmux.sim.v"

`include "routing/N5ffmux/a5ffmux.sim.v"
`include "routing/N5ffmux/b5ffmux.sim.v"
`include "routing/N5ffmux/c5ffmux.sim.v"
`include "routing/N5ffmux/d5ffmux.sim.v"

`include "routing/Ncy0/acy0.sim.v"
`include "routing/Ncy0/bcy0.sim.v"
`include "routing/Ncy0/ccy0.sim.v"
`include "routing/Ncy0/dcy0.sim.v"

`include "routing/Nused/aused.sim.v"
`include "routing/Nused/bused.sim.v"
`include "routing/Nused/cused.sim.v"
`include "routing/Nused/dused.sim.v"

`include "carry/carry4_vpr.sim.v"

`include "routing/clkinv/clkinv.sim.v"

// Broken
module COMMON_SLICE(
	DX, D1, D2, D3, D4, D5, D6, DMUX, D, DQ,	// D port
	CX, C1, C2, C3, C4, C5, C6, CMUX, C, CQ,	// C port
	BX, B1, B2, B3, B4, B5, B6, BMUX, B, BQ,	// B port
	AX, A1, A2, A3, A4, A5, A6, AMUX, A, AQ,	// A port
	SR, CE, CLK, 		// Flip flop signals
	CIN, CYINIT, COUT,	// Carry to/from adjacent slices
);
	// D port
	input wire DX;
	input wire D1;
	input wire D2;
	input wire D3;
	input wire D4;
	input wire D5;
	input wire D6;
	output wire DMUX;
	output wire D;
	output wire DQ;

	// D port flip-flop config
	parameter D5FF_SRVAL		= "SRLOW";
	parameter D5FF_INIT		= D5FF_SRVAL;
	parameter DFF_SRVAL		= "SRLOW";
	parameter DFF_INIT		= D5FF_SRVAL;

	// C port
	input wire CX;
	input wire C1;
	input wire C2;
	input wire C3;
	input wire C4;
	input wire C5;
	input wire C6;
	output wire CMUX;
	output wire C;
	output wire CQ;

	// B port
	input wire BX;
	input wire B1;
	input wire B2;
	input wire B3;
	input wire B4;
	input wire B5;
	input wire B6;
	output wire BMUX;
	output wire B;
	output wire BQ;

	// A port
	input wire AX;
	input wire A1;
	input wire A2;
	input wire A3;
	input wire A4;
	input wire A5;
	input wire A6;
	output wire AMUX;
	output wire A;
	output wire AQ;

	// Shared Flip flop signals
	input wire CLK; // Clock
	input wire SR;	// Set/Reset
	input wire CE;	// Clock enable

	// Reset type for all flip flops, can be;
	// * None  -- Ignore SR
	// * Sync  -- Reset occurs on clock edge
	// * Async -- Reset occurs when ever
	parameter SR_TYPE = "SYNC";

	// The mode this unit operates in, can be;
	// "FLIPFLOP" 	- Operate as a flip-flop (D->Q on clock low->high)
	// "LATCH" 	- Operate as a latch	 (D->Q while CLK low)
	parameter FF_MODE = "FLIPFLOP";

	// Carry to/from adjacent slices
	input wire CIN;
	input wire CYINIT;
	output wire COUT;

	// Internal routing configuration
	wire A5LUT_O5;
	wire B5LUT_O5;
	wire C5LUT_O5;
	wire D5LUT_O5;
	wire D6LUT_O6;
	wire C6LUT_O6;
	wire B6LUT_O6;
	wire A6LUT_O6;

	ALUT alut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .O6(A6LUT_O6), .O5(A5LUT_O5));
	BLUT blut (.A1(B1), .A2(B2), .A3(B3), .A4(B4), .A5(B5), .A6(B6), .O6(B6LUT_O6), .O5(B5LUT_O5));
	CLUT clut (.A1(C1), .A2(C2), .A3(C3), .A4(C4), .A5(C5), .A6(C6), .O6(C6LUT_O6), .O5(C5LUT_O5));
	DLUT dlut (.A1(D1), .A2(D2), .A3(D3), .A4(D4), .A5(D5), .A6(D6), .O6(D6LUT_O6), .O5(D5LUT_O5));

	wire F7AMUX_OUT;
	wire F8MUX_OUT;

	wire A5FFMUX_OUT;
	wire B5FFMUX_OUT;
	wire C5FFMUX_OUT;
	wire D5FFMUX_OUT;

	A5FFMUX a5ffmux (.IN_B(AX), .IN_A(A5LUT_O5), .O(A5FFMUX_OUT));
	B5FFMUX b5ffmux (.IN_B(BX), .IN_A(B5LUT_O5), .O(B5FFMUX_OUT));
	C5FFMUX c5ffmux (.IN_B(CX), .IN_A(C5LUT_O5), .O(C5FFMUX_OUT));
	D5FFMUX d5ffmux (.IN_B(DX), .IN_A(D5LUT_O5), .O(D5FFMUX_OUT));

	wire ACY0_OUT;
	wire BCY0_OUT;
	wire CCY0_OUT;
	wire DCY0_OUT;

	ACY0 acy0 (.O5(A5LUT_O5), .AX(AX), .O(ACY0_OUT));
	BCY0 bcy0 (.O5(B5LUT_O5), .BX(BX), .O(BCY0_OUT));
	CCY0 ccy0 (.O5(C5LUT_O5), .CX(CX), .O(CCY0_OUT));
	DCY0 dcy0 (.O5(D5LUT_O5), .DX(DX), .O(DCY0_OUT));

	wire F7BMUX_OUT;
	F7BMUX f7bmux (.I0(D6LUT_O6), .I1(C6LUT_O6), .OUT(F7BMUX_OUT), .S0(CX));
	wire F7AMUX_OUT;
	F7BMUX f7amux (.I0(B6LUT_O6), .I1(A6LUT_O6), .OUT(F7AMUX_OUT), .S0(AX));
	wire F8MUX_OUT;
	F8MUX f8mux (.I0(F7BMUX_OUT), .I1(F7AMUX_OUT), .OUT(F8MUX_OUT), .S0(BX));

	wire PRECYINIT_OUT;
	PRECYINIT_MUX precyinit_mux (.C0(0), .C1(1), .CI(CIN), .CYINIT(CYINIT), .OUT(PRECYINIT_OUT));

	wire [3:0] CARRY4_CO;
	wire [3:0] CARRY4_O;

	CARRY4_MODES carry4 (
		.CO(CARRY4_CO),
		.O(CARRY4_O),
		.DI({ACY0_OUT, BCY0_OUT, CCY0_OUT, DCY0_OUT}),
		.S({A6LUT_O6, B6LUT_O6, C6LUT_O6, D6LUT_O6}),
		.CIN(PRECYINIT_OUT));

	COUTUSED coutused (.IN(CARRY4_O[3]), .OUT(COUT));

	wire A5FF_Q;
	wire B5FF_Q;
	wire C5FF_Q;
	wire D5FF_Q;

	AOUTMUX aoutmux (
		.A5Q(A5FF_Q), .XOR(CARRY4_O[0]), .O6(A6LUT_O6), .O5(A5LUT_O5), .CY(CARRY4_CO[0]), .F7(F7AMUX_OUT),
		.OUT(AMUX));
	BOUTMUX boutmux (
		.B5Q(B5FF_Q), .XOR(CARRY4_O[1]), .O6(B6LUT_O6), .O5(B5LUT_O5), .CY(CARRY4_CO[1]), .F8(F8MUX_OUT),
		.OUT(BMUX));
	COUTMUX coutmux (
		.C5Q(C5FF_Q), .XOR(CARRY4_O[2]), .O6(C6LUT_O6), .O5(C5LUT_O5), .CY(CARRY4_CO[2]), .F7(F7BMUX_OUT),
		.OUT(CMUX));
	DOUTMUX doutmux (
		.D5Q(D5FF_Q), .XOR(CARRY4_O[3]), .O6(D6LUT_O6), .O5(D5LUT_O5), .CY(CARRY4_CO[3]),
		.OUT(DMUX));

	wire AFFMUX_OUT;
	wire BFFMUX_OUT;
	wire CFFMUX_OUT;
	wire DFFMUX_OUT;

	AFFMUX affmux (
		.AX(AX), .XOR(CARRY4_O[0]), .O6(A6LUT_O6), .O5(A5LUT_O5), .CY(CARRY4_CO[0]), .F7(F7AMUX_OUT),
		.OUT(AFFMUX_OUT));
	BFFMUX bffmux (
		.BX(BX), .XOR(CARRY4_O[1]), .O6(B6LUT_O6), .O5(B5LUT_O5), .CY(CARRY4_CO[1]), .F8(F8MUX_OUT),
		.OUT(BFFMUX_OUT));
	CFFMUX cffmux (
		.CX(CX), .XOR(CARRY4_O[2]), .O6(C6LUT_O6), .O5(C5LUT_O5), .CY(CARRY4_CO[2]), .F7(F7BMUX_OUT),
		.OUT(CFFMUX_OUT));
	DFFMUX dffmux (
		.DX(DX), .XOR(CARRY4_O[3]), .O6(D6LUT_O6), .O5(D5LUT_O5), .CY(CARRY4_CO[3]),
		.OUT(DFFMUX_OUT));

	wire CEUSEDMUX_OUT;
	wire SRUSEDMUX_OUT;
	wire CLKINV_OUT;

	CLKINV clkinv (.CLK(CLK), .OUT(CLKINV_OUT));

	A5FF a5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(A5FFMUX_OUT), .Q(A5FF_Q));
	B5FF b5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(B5FFMUX_OUT), .Q(B5FF_Q));
	C5FF c5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(C5FFMUX_OUT), .Q(C5FF_Q));
	D5FF d5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(D5FFMUX_OUT), .Q(D5FF_Q));

	A5FF aff  (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(AFFMUX_OUT),  .Q(AQ));
	B5FF bff  (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(BFFMUX_OUT),  .Q(BQ));
	C5FF cff  (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(CFFMUX_OUT),  .Q(CQ));
	D5FF dff  (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(DFFMUX_OUT),  .Q(DQ));

	AUSED aused (.I0(A6LUT_O6), .O(A));
	BUSED bused (.I0(B6LUT_O6), .O(B));
	CUSED cused (.I0(C6LUT_O6), .O(C));
	DUSED dused (.I0(D6LUT_O6), .O(D));

	CEUSEDMUX ceusedmux (.IN(CE), .OUT(CEUSEDMUX_OUT));
	SRUSEDMUX srusedmux (.IN(SR), .OUT(SRUSEDMUX_OUT));

endmodule

Physical Block XML

<!-- A diagram for the SLICEL is shown in;
    7 Series FPGAs CLB User Guide UG474 (v1.8) September 27, 2016
    Figure 2-4: Diagram of SLICEL

    COMMON_SLICE is the common wiring between SLICEL and SLICEM.

    Note: For SLICEL, the AMC31 input is left unconnected.
  -->
<pb_type name="COMMON_SLICE" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">

  <input name="DX" num_pins="1"/>
  <input name="CX" num_pins="1"/>
  <input name="BX" num_pins="1"/>
  <input name="AX" num_pins="1"/>

  <input name="DO6" num_pins="1"/>
  <input name="CO6" num_pins="1"/>
  <input name="BO6" num_pins="1"/>
  <input name="AO6" num_pins="1"/>

  <input name="DO5" num_pins="1"/>
  <input name="CO5" num_pins="1"/>
  <input name="BO5" num_pins="1"/>
  <input name="AO5" num_pins="1"/>

  <input name="SR" num_pins="1"/>
  <input name="CE" num_pins="1"/>

  <input name="F7AMUX_O" num_pins="1"/>
  <input name="F7BMUX_O" num_pins="1"/>
  <input name="F8MUX_O" num_pins="1"/>

  <!-- This input in unconnected on SLICEL -->
  <input name="AMC31" num_pins="1"/>

  <clock name="CLK" num_pins="1"/>

  <input  name="CIN"  num_pins="1"/>
  <output name="COUT" num_pins="1"/>

  <output name="DMUX" num_pins="1"/>
  <output name="D"    num_pins="1"/>
  <output name="DQ"   num_pins="1"/>

  <output name="CMUX" num_pins="1"/>
  <output name="C"    num_pins="1"/>
  <output name="CQ"   num_pins="1"/>

  <output name="BMUX" num_pins="1"/>
  <output name="B"    num_pins="1"/>
  <output name="BQ"   num_pins="1"/>

  <output name="AMUX" num_pins="1"/>
  <output name="A"    num_pins="1"/>
  <output name="AQ"   num_pins="1"/>


  <xi:include href="../ff/ff.pb_type.xml" />

  <!-- CARRY4 logic -->
  <xi:include href="carry/carry4_vpr.pb_type.xml" />

  <pb_type name="CEUSEDMUX" num_pb="1" >
    <input name="CE" num_pins="1" />
    <output name="CE_OUT" num_pins="8" />

    <mode name="CE_VCC">
      <pb_type name="CE_VCC" blif_model=".subckt CE_VCC" num_pb="8" >
        <output name="VCC" num_pins="1" />
      </pb_type>
      <interconnect>
        <direct name="CE0" input="CE_VCC[0].VCC" output="CEUSEDMUX.CE_OUT[0]" >
          <pack_pattern name="CE_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="CE_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="CE_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="CE_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="CE1" input="CE_VCC[1].VCC" output="CEUSEDMUX.CE_OUT[1]" >
          <pack_pattern name="CE_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="CE_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="CE_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="CE_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="CE2" input="CE_VCC[2].VCC" output="CEUSEDMUX.CE_OUT[2]" >
          <pack_pattern name="CE_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="CE_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="CE_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="CE_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="CE3" input="CE_VCC[3].VCC" output="CEUSEDMUX.CE_OUT[3]" >
          <pack_pattern name="CE_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="CE_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="CE_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="CE_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="CE4" input="CE_VCC[4].VCC" output="CEUSEDMUX.CE_OUT[4]" >
          <pack_pattern name="CE_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="CE_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="CE_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="CE_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="CE5" input="CE_VCC[5].VCC" output="CEUSEDMUX.CE_OUT[5]" >
          <pack_pattern name="CE_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="CE_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="CE_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="CE_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="CE6" input="CE_VCC[6].VCC" output="CEUSEDMUX.CE_OUT[6]" >
          <pack_pattern name="CE_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="CE_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="CE_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="CE_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="CE7" input="CE_VCC[7].VCC" output="CEUSEDMUX.CE_OUT[7]" >
          <pack_pattern name="CE_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="CE_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="CE_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="CE_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
      </interconnect>
    </mode>
    <mode name="CEUSEDMUX">
      <interconnect>
        <complete name="CE" input="CEUSEDMUX.CE" output="CEUSEDMUX.CE_OUT" />
      </interconnect>
    </mode>
  </pb_type>

  <pb_type name="SRUSEDMUX" num_pb="1">
    <input name="SR" num_pins="1" />
    <output name="SR_OUT" num_pins="8" />


    <mode name="SR_GND">
      <pb_type name="SR_GND" blif_model=".subckt SR_GND" num_pb="8" >
        <output name="GND" num_pins="1" />
      </pb_type>
      <interconnect>
        <direct name="SR0" input="SR_GND[0].GND" output="SRUSEDMUX.SR_OUT[0]" >
          <pack_pattern name="SR_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="SR_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="SR_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="SR_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="SR1" input="SR_GND[1].GND" output="SRUSEDMUX.SR_OUT[1]" >
          <pack_pattern name="SR_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="SR_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="SR_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="SR_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="SR2" input="SR_GND[2].GND" output="SRUSEDMUX.SR_OUT[2]" >
          <pack_pattern name="SR_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="SR_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="SR_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="SR_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="SR3" input="SR_GND[3].GND" output="SRUSEDMUX.SR_OUT[3]" >
          <pack_pattern name="SR_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="SR_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="SR_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="SR_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="SR4" input="SR_GND[4].GND" output="SRUSEDMUX.SR_OUT[4]" >
          <pack_pattern name="SR_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="SR_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="SR_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="SR_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="SR5" input="SR_GND[5].GND" output="SRUSEDMUX.SR_OUT[5]" >
          <pack_pattern name="SR_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="SR_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="SR_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="SR_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="SR6" input="SR_GND[6].GND" output="SRUSEDMUX.SR_OUT[6]" >
          <pack_pattern name="SR_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="SR_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="SR_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="SR_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
        <direct name="SR7" input="SR_GND[7].GND" output="SRUSEDMUX.SR_OUT[7]" >
          <pack_pattern name="SR_FF_FDSE"/>
          <pack_pattern name="CESR_FF_FDSE"/>
          <pack_pattern name="SR_FF_FDRE"/>
          <pack_pattern name="CESR_FF_FDRE"/>
          <pack_pattern name="SR_FF_FDPE"/>
          <pack_pattern name="CESR_FF_FDPE"/>
          <pack_pattern name="SR_FF_FDCE"/>
          <pack_pattern name="CESR_FF_FDCE"/>
        </direct>
      </interconnect>
    </mode>
    <mode name="SRUSEDMUX">
      <interconnect>
        <complete name="SR" input="SRUSEDMUX.SR" output="SRUSEDMUX.SR_OUT" />
      </interconnect>
    </mode>
  </pb_type>

  <interconnect>
    <!-- 5FF MUXs -->
    <mux name="D5FFMUX" input="COMMON_SLICE.DX COMMON_SLICE.DO5" output="SLICE_FF.D5[3]" >
      <delay_constant in_port="COMMON_SLICE.DX"  max="{interconnect_dx_d5ffl}" out_port="SLICE_FF.D5[3]" />
      <delay_constant in_port="COMMON_SLICE.DO5" max="{interconnect_d5lut_d5ffl}"    out_port="SLICE_FF.D5[3]" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.DO5 = D5FFMUX.IN_A
          COMMON_SLICE.DX = D5FFMUX.IN_B
        </meta>
      </metadata>
    </mux>
    <mux name="C5FFMUX" input="COMMON_SLICE.CX COMMON_SLICE.CO5" output="SLICE_FF.D5[2]" >
      <delay_constant in_port="COMMON_SLICE.CX"  max="{interconnect_cx_c5ffl}" out_port="SLICE_FF.D5[2]" />
      <delay_constant in_port="COMMON_SLICE.CO5" max="{interconnect_c5lut_c5ffl}"    out_port="SLICE_FF.D5[2]" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.CO5 = C5FFMUX.IN_A
          COMMON_SLICE.CX = C5FFMUX.IN_B
        </meta>
      </metadata>
    </mux>
    <mux name="B5FFMUX" input="COMMON_SLICE.BX COMMON_SLICE.BO5" output="SLICE_FF.D5[1]" >
      <delay_constant in_port="COMMON_SLICE.BX"  max="{interconnect_bx_b5ffl}" out_port="SLICE_FF.D5[1]" />
      <delay_constant in_port="COMMON_SLICE.BO5" max="{interconnect_b5lut_b5ffl}"    out_port="SLICE_FF.D5[1]" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.BO5 = B5FFMUX.IN_A
          COMMON_SLICE.BX = B5FFMUX.IN_B
        </meta>
      </metadata>
    </mux>
    <mux name="A5FFMUX" input="COMMON_SLICE.AX COMMON_SLICE.AO5" output="SLICE_FF.D5[0]" >
      <delay_constant in_port="COMMON_SLICE.AX"  max="{interconnect_ax_a5ffl}" out_port="SLICE_FF.D5[0]" />
      <delay_constant in_port="COMMON_SLICE.AO5" max="{interconnect_a5lut_a5ffl}"    out_port="SLICE_FF.D5[0]" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.AO5 = A5FFMUX.IN_A
          COMMON_SLICE.AX = A5FFMUX.IN_B
        </meta>
      </metadata>
    </mux>

    <!-- [A-D]MUX -->
    <mux name="DOUTMUX"
      input="COMMON_SLICE.AMC31 SLICE_FF.Q5[3] CARRY4_VPR.O3 CARRY4_VPR.CO_FABRIC3 COMMON_SLICE.DO6 COMMON_SLICE.DO5"
      output="COMMON_SLICE.DMUX">
      <delay_constant in_port="SLICE_FF.Q5[3]" max="{interconnect_d5ff_dmux}" out_port="COMMON_SLICE.DMUX" />
      <delay_constant in_port="CARRY4_VPR.O3" max="{interconnect_carry4_co3_dmux}" out_port="COMMON_SLICE.DMUX" />
      <delay_constant in_port="CARRY4_VPR.CO_FABRIC3" max="{interconnect_carry4_o3_dmux}" out_port="COMMON_SLICE.DMUX" />
      <delay_constant in_port="COMMON_SLICE.DO6" max="{interconnect_d6lut_dmux}" out_port="COMMON_SLICE.DMUX" />
      <delay_constant in_port="COMMON_SLICE.DO5" max="{interconnect_d5lut_dmux}" out_port="COMMON_SLICE.DMUX" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.AMC31 = DOUTMUX.MC31
          SLICE_FF.Q5[3] = DOUTMUX.D5Q
          COMMON_SLICE.DO5 = DOUTMUX.O5
          COMMON_SLICE.DO6 = DOUTMUX.O6
          CARRY4_VPR.CO_FABRIC3 = DOUTMUX.CY
          CARRY4_VPR.O3 = DOUTMUX.XOR
        </meta>
      </metadata>
    </mux>
    <mux name="COUTMUX"
      input="SLICE_FF.Q5[2] CARRY4_VPR.O2 CARRY4_VPR.CO_FABRIC2 COMMON_SLICE.CO6 COMMON_SLICE.CO5 COMMON_SLICE.F7BMUX_O"
      output="COMMON_SLICE.CMUX" >
      <delay_constant in_port="SLICE_FF.Q5[2]" max="{interconnect_c5ff_cmux}" out_port="COMMON_SLICE.CMUX" />
      <delay_constant in_port="CARRY4_VPR.O2" max="{interconnect_carry4_co2_cmux}" out_port="COMMON_SLICE.CMUX" />
      <delay_constant in_port="CARRY4_VPR.CO_FABRIC2" max="{interconnect_carry4_o2_cmux}" out_port="COMMON_SLICE.CMUX" />
      <delay_constant in_port="COMMON_SLICE.CO6" max="{interconnect_c6lut_cmux}" out_port="COMMON_SLICE.CMUX" />
      <delay_constant in_port="COMMON_SLICE.CO5" max="{interconnect_c5lut_cmux}" out_port="COMMON_SLICE.CMUX" />
      <metadata>
        <meta name="fasm_mux">
          SLICE_FF.Q5[2] = COUTMUX.C5Q
          COMMON_SLICE.F7BMUX_O = COUTMUX.F7
          COMMON_SLICE.CO5 = COUTMUX.O5
          COMMON_SLICE.CO6 = COUTMUX.O6
          CARRY4_VPR.CO_FABRIC2 = COUTMUX.CY
          CARRY4_VPR.O2 = COUTMUX.XOR
        </meta>
      </metadata>
    </mux>
    <mux name="BOUTMUX"
      input="SLICE_FF.Q5[1] CARRY4_VPR.O1 CARRY4_VPR.CO_FABRIC1 COMMON_SLICE.BO6 COMMON_SLICE.BO5 COMMON_SLICE.F8MUX_O"
      output="COMMON_SLICE.BMUX" >
      <delay_constant in_port="SLICE_FF.Q5[1]" max="{interconnect_b5ff_bmux}" out_port="COMMON_SLICE.BMUX" />
      <delay_constant in_port="CARRY4_VPR.O1" max="{interconnect_carry4_co1_bmux}" out_port="COMMON_SLICE.BMUX" />
      <delay_constant in_port="CARRY4_VPR.CO_FABRIC1" max="{interconnect_carry4_o1_bmux}" out_port="COMMON_SLICE.BMUX" />
      <delay_constant in_port="COMMON_SLICE.BO6" max="{interconnect_b6lut_bmux}" out_port="COMMON_SLICE.BMUX" />
      <delay_constant in_port="COMMON_SLICE.BO5" max="{interconnect_b5lut_bmux}" out_port="COMMON_SLICE.BMUX" />
      <metadata>
        <meta name="fasm_mux">
          SLICE_FF.Q5[1] = BOUTMUX.B5Q
          COMMON_SLICE.F8MUX_O = BOUTMUX.F8
          COMMON_SLICE.BO5 = BOUTMUX.O5
          COMMON_SLICE.BO6 = BOUTMUX.O6
          CARRY4_VPR.CO_FABRIC1 = BOUTMUX.CY
          CARRY4_VPR.O1 = BOUTMUX.XOR
        </meta>
      </metadata>
    </mux>
    <mux name="AOUTMUX"
      input="SLICE_FF.Q5[0] CARRY4_VPR.O0 CARRY4_VPR.CO_FABRIC0 COMMON_SLICE.AO6 COMMON_SLICE.AO5 COMMON_SLICE.F7AMUX_O"
      output="COMMON_SLICE.AMUX" >
      <delay_constant in_port="SLICE_FF.Q5[0]" max="{interconnect_a5ff_amux}" out_port="COMMON_SLICE.AMUX" />
      <delay_constant in_port="CARRY4_VPR.O0" max="{interconnect_carry4_co0_amux}" out_port="COMMON_SLICE.AMUX" />
      <delay_constant in_port="CARRY4_VPR.CO_FABRIC0" max="{interconnect_carry4_o0_amux}" out_port="COMMON_SLICE.AMUX" />
      <delay_constant in_port="COMMON_SLICE.AO6" max="{interconnect_a6lut_amux}" out_port="COMMON_SLICE.AMUX" />
      <delay_constant in_port="COMMON_SLICE.AO5" max="{interconnect_a5lut_amux}" out_port="COMMON_SLICE.AMUX" />
      <metadata>
        <meta name="fasm_mux">
          SLICE_FF.Q5[0] = AOUTMUX.A5Q
          COMMON_SLICE.F7AMUX_O = AOUTMUX.F7
          COMMON_SLICE.AO5 = AOUTMUX.O5
          COMMON_SLICE.AO6 = AOUTMUX.O6
          CARRY4_VPR.CO_FABRIC0 = AOUTMUX.CY
          CARRY4_VPR.O0 = AOUTMUX.XOR
        </meta>
      </metadata>
    </mux>

    <!-- [A-D]FFMUX -->
    <mux name="DFFMUX"
      input="COMMON_SLICE.AMC31 CARRY4_VPR.O3 CARRY4_VPR.CO_FABRIC3 COMMON_SLICE.DO6 COMMON_SLICE.DO5 COMMON_SLICE.DX"
      output="SLICE_FF.D[3]" >
      <delay_constant in_port="COMMON_SLICE.DX" max="{interconnect_dx_dff}" out_port="SLICE_FF.D[3]" />
      <delay_constant in_port="COMMON_SLICE.DO5" max="{interconnect_d5lut_dff}" out_port="SLICE_FF.D[3]" />
      <delay_constant in_port="COMMON_SLICE.DO6" max="{interconnect_d6lut_dff}" out_port="SLICE_FF.D[3]" />
      <delay_constant in_port="CARRY4_VPR.CO_FABRIC3" max="{interconnect_carry4_co3_dff}" out_port="SLICE_FF.D[3]" />
      <delay_constant in_port="CARRY4_VPR.O3" max="{interconnect_carry4_o3_dff}" out_port="SLICE_FF.D[3]" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.AMC31 = DFFMUX.MC31
          COMMON_SLICE.DX = DFFMUX.DX
          COMMON_SLICE.DO5 = DFFMUX.O5
          COMMON_SLICE.DO6 = DFFMUX.O6
          CARRY4_VPR.CO_FABRIC3 = DFFMUX.CY
          CARRY4_VPR.O3 = DFFMUX.XOR
        </meta>
      </metadata>
    </mux>
    <mux name="CFFMUX"
      input="CARRY4_VPR.O2 CARRY4_VPR.CO_FABRIC2 COMMON_SLICE.CO6 COMMON_SLICE.CO5 COMMON_SLICE.CX COMMON_SLICE.F7BMUX_O"
      output="SLICE_FF.D[2]" >
      <delay_constant in_port="COMMON_SLICE.CX" max="{interconnect_cx_cff}" out_port="SLICE_FF.D[2]" />
      <delay_constant in_port="COMMON_SLICE.F7BMUX_O" max="{interconnect_f7bmux_cff}" out_port="SLICE_FF.D[2]" />
      <delay_constant in_port="COMMON_SLICE.CO5" max="{interconnect_c5lut_cff}" out_port="SLICE_FF.D[2]" />
      <delay_constant in_port="COMMON_SLICE.CO6" max="{interconnect_c6lut_cff}" out_port="SLICE_FF.D[2]" />
      <delay_constant in_port="CARRY4_VPR.CO_FABRIC2" max="{interconnect_carry4_co2_cff}" out_port="SLICE_FF.D[2]" />
      <delay_constant in_port="CARRY4_VPR.O2" max="{interconnect_carry4_o2_cff}" out_port="SLICE_FF.D[2]" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.CX = CFFMUX.CX
          COMMON_SLICE.F7BMUX_O = CFFMUX.F7
          COMMON_SLICE.CO5 = CFFMUX.O5
          COMMON_SLICE.CO6 = CFFMUX.O6
          CARRY4_VPR.CO_FABRIC2 = CFFMUX.CY
          CARRY4_VPR.O2 = CFFMUX.XOR
        </meta>
      </metadata>
    </mux>
    <mux name="BFFMUX"
      input="CARRY4_VPR.O1 CARRY4_VPR.CO_FABRIC1 COMMON_SLICE.BO6 COMMON_SLICE.BO5 COMMON_SLICE.BX COMMON_SLICE.F8MUX_O"
      output="SLICE_FF.D[1]" >
      <delay_constant in_port="COMMON_SLICE.BX" max="{interconnect_bx_bff}" out_port="SLICE_FF.D[1]" />
      <delay_constant in_port="COMMON_SLICE.F8MUX_O" max="{interconnect_f8mux_bff}" out_port="SLICE_FF.D[1]" />
      <delay_constant in_port="COMMON_SLICE.BO5" max="{interconnect_b5lut_bff}" out_port="SLICE_FF.D[1]" />
      <delay_constant in_port="COMMON_SLICE.BO6" max="{interconnect_b6lut_bff}" out_port="SLICE_FF.D[1]" />
      <delay_constant in_port="CARRY4_VPR.CO_FABRIC1" max="{interconnect_carry4_co1_bff}" out_port="SLICE_FF.D[1]" />
      <delay_constant in_port="CARRY4_VPR.O1" max="{interconnect_carry4_o1_bff}" out_port="SLICE_FF.D[1]" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.BX = BFFMUX.BX
          COMMON_SLICE.F8MUX_O = BFFMUX.F8
          COMMON_SLICE.BO5 = BFFMUX.O5
          COMMON_SLICE.BO6 = BFFMUX.O6
          CARRY4_VPR.CO_FABRIC1 = BFFMUX.CY
          CARRY4_VPR.O1 = BFFMUX.XOR
        </meta>
      </metadata>
    </mux>
    <mux name="AFFMUX"
      input="CARRY4_VPR.O0 CARRY4_VPR.CO_FABRIC0 COMMON_SLICE.AO6 COMMON_SLICE.AO5 COMMON_SLICE.AX COMMON_SLICE.F7AMUX_O"
      output="SLICE_FF.D[0]" >
      <delay_constant in_port="COMMON_SLICE.AX" max="{interconnect_ax_aff}" out_port="SLICE_FF.D[0]" />
      <delay_constant in_port="COMMON_SLICE.F7AMUX_O" max="{interconnect_f7amux_aff}" out_port="SLICE_FF.D[0]" />
      <delay_constant in_port="COMMON_SLICE.AO5" max="{interconnect_a5lut_aff}" out_port="SLICE_FF.D[0]" />
      <delay_constant in_port="COMMON_SLICE.AO6" max="{interconnect_a6lut_aff}" out_port="SLICE_FF.D[0]" />
      <delay_constant in_port="CARRY4_VPR.CO_FABRIC0" max="{interconnect_carry4_co0_aff}" out_port="SLICE_FF.D[0]" />
      <delay_constant in_port="CARRY4_VPR.O0" max="{interconnect_carry4_o0_aff}" out_port="SLICE_FF.D[0]" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.AX = AFFMUX.AX
          COMMON_SLICE.F7AMUX_O = AFFMUX.F7
          COMMON_SLICE.AO5 = AFFMUX.O5
          COMMON_SLICE.AO6 = AFFMUX.O6
          CARRY4_VPR.CO_FABRIC0 = AFFMUX.CY
          CARRY4_VPR.O0 = AFFMUX.XOR
        </meta>
      </metadata>
    </mux>

    <!-- [A-F]Q outputs -->
    <direct name="AFF" input="SLICE_FF.Q[0]" output="COMMON_SLICE.AQ" />
    <direct name="BFF" input="SLICE_FF.Q[1]" output="COMMON_SLICE.BQ" />
    <direct name="CFF" input="SLICE_FF.Q[2]" output="COMMON_SLICE.CQ" />
    <direct name="DFF" input="SLICE_FF.Q[3]" output="COMMON_SLICE.DQ" />

    <!-- LUT O6 output -->
    <direct name="COMMON_SLICE_DOUT" input="COMMON_SLICE.DO6" output="COMMON_SLICE.D" >
      <delay_constant in_port="COMMON_SLICE.DO6" max="{interconnect_d6lut_d}" out_port="COMMON_SLICE.D" />
    </direct>
    <direct name="COMMON_SLICE_COUT" input="COMMON_SLICE.CO6" output="COMMON_SLICE.C" >
      <delay_constant in_port="COMMON_SLICE.CO6" max="{interconnect_c6lut_c}" out_port="COMMON_SLICE.C" />
    </direct>
    <direct name="COMMON_SLICE_BOUT" input="COMMON_SLICE.BO6" output="COMMON_SLICE.B" >
      <delay_constant in_port="COMMON_SLICE.BO6" max="{interconnect_b6lut_b}" out_port="COMMON_SLICE.B" />
    </direct>
    <direct name="COMMON_SLICE_AOUT" input="COMMON_SLICE.AO6" output="COMMON_SLICE.A" >
      <delay_constant in_port="COMMON_SLICE.AO6" max="{interconnect_a6lut_a}" out_port="COMMON_SLICE.A" />
    </direct>

    <!-- Carry -->

    <!-- Carry initialization -->
    <direct name="PRECYINIT_MUX"
      input="COMMON_SLICE.AX"
      output="CARRY4_VPR.CYINIT">
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.AX = PRECYINIT.AX
        </meta>
      </metadata>
    </direct>

    <direct name="CIN_TO_CARRY0" input="COMMON_SLICE.CIN" output="CARRY4_VPR.CIN" >
      <pack_pattern name="CARRYCHAIN"/>
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.CIN = PRECYINIT.CIN
        </meta>
      </metadata>
    </direct>

    <!-- Carry selects -->
    <direct name="CARRY_S3" input="COMMON_SLICE.DO6" output="CARRY4_VPR.S3" />
    <direct name="CARRY_S2" input="COMMON_SLICE.CO6" output="CARRY4_VPR.S2" />
    <direct name="CARRY_S1" input="COMMON_SLICE.BO6" output="CARRY4_VPR.S1" />
    <direct name="CARRY_S0" input="COMMON_SLICE.AO6" output="CARRY4_VPR.S0" />

    <!-- Carry MUXCY.DI -->
    <mux name="CARRY_DI3" input="COMMON_SLICE.DO5 COMMON_SLICE.DX" output="CARRY4_VPR.DI3" >
      <delay_constant max=".058e-9" in_port="DX" out_port="CARRY4_VPR.DI3" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.DO5 = CARRY4.DCY0
          COMMON_SLICE.DX = NULL
        </meta>
      </metadata>
    </mux>
    <mux name="CARRY_DI2" input="COMMON_SLICE.CO5 COMMON_SLICE.CX" output="CARRY4_VPR.DI2" >
      <delay_constant max=".094e-9" in_port="CX" out_port="CARRY4_VPR.DI2" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.CO5 = CARRY4.CCY0
          COMMON_SLICE.CX = NULL
        </meta>
      </metadata>
    </mux>
    <mux name="CARRY_DI1" input="COMMON_SLICE.BO5 COMMON_SLICE.BX" output="CARRY4_VPR.DI1" >
      <delay_constant max=".085e-9" in_port="BX" out_port="CARRY4_VPR.DI1" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.BO5 = CARRY4.BCY0
          COMMON_SLICE.BX = NULL
        </meta>
      </metadata>
    </mux>
    <mux name="CARRY_DI0" input="COMMON_SLICE.AO5 COMMON_SLICE.AX" output="CARRY4_VPR.DI0" >
      <delay_constant max=".105e-9" in_port="AX" out_port="CARRY4_VPR.DI0" />
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.AO5 = CARRY4.ACY0
          COMMON_SLICE.AX = NULL
        </meta>
      </metadata>
    </mux>

    <direct name="COUT" input="CARRY4_VPR.CO_CHAIN" output="COMMON_SLICE.COUT" >
      <pack_pattern name="CARRYCHAIN"/>
      <delay_constant in_port="CARRY4_VPR.CO_CHAIN" max="{interconnect_carry4_co3_cout}" out_port="COMMON_SLICE.COUT" />
    </direct>

    <!-- Clock, Clock Enable and Reset -->
    <direct name="CK" input="COMMON_SLICE.CLK" output="SLICE_FF.CK"/>

    <direct name="CE" input="COMMON_SLICE.CE" output="CEUSEDMUX.CE" >
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.CE = CEUSEDMUX
        </meta>
      </metadata>
    </direct>
    <direct name="CE_OUT"
      input="CEUSEDMUX.CE_OUT"
      output="SLICE_FF.CE"
      />

    <direct name="SR" input="COMMON_SLICE.SR"  output="SRUSEDMUX.SR" >
      <metadata>
        <meta name="fasm_mux">
          COMMON_SLICE.SR = SRUSEDMUX
        </meta>
      </metadata>
    </direct>
    <direct name="SR_OUT"
      input="SRUSEDMUX.SR_OUT"
      output="SLICE_FF.SR"
      />

  </interconnect>
  <metadata>
    <meta name="type">block</meta>
    <meta name="subtype">ignore</meta>
  </metadata>
</pb_type>

Model XML

<models xmlns:xi="http://www.w3.org/2001/XInclude">
  <model name="CE_VCC">
    <output_ports>
      <port name="VCC" />
    </output_ports>
  </model>
  <model name="SR_GND">
    <output_ports>
      <port name="GND" />
    </output_ports>
  </model>
  <xi:include href="carry/carry4_vpr.model.xml"    xpointer="xpointer(models/child::node())" />
  <xi:include href="../ff/ff.model.xml"            xpointer="xpointer(models/child::node())" />
</models>