carry4_vpr¶
Component Diagram¶
Internal Diagram¶
Verilog File¶
(* whitebox *)
module CARRY4_VPR(O0, O1, O2, O3, CO_CHAIN, CO_FABRIC0, CO_FABRIC1, CO_FABRIC2, CO_FABRIC3, CYINIT, CIN, DI0, DI1, DI2, DI3, S0, S1, S2, S3);
parameter CYINIT_AX = 1'b0;
parameter CYINIT_C0 = 1'b0;
parameter CYINIT_C1 = 1'b0;
(* DELAY_CONST_CYINIT="0.491e-9" *)
(* DELAY_CONST_CIN="0.235e-9" *)
(* DELAY_CONST_S0="0.223e-9" *)
output wire O0;
(* DELAY_CONST_CYINIT="0.613e-9" *)
(* DELAY_CONST_CIN="0.348e-9" *)
(* DELAY_CONST_S0="0.400e-9" *)
(* DELAY_CONST_S1="0.205e-9" *)
(* DELAY_CONST_DI0="0.337e-9" *)
output wire O1;
(* DELAY_CONST_CYINIT="0.600e-9" *)
(* DELAY_CONST_CIN="0.256e-9" *)
(* DELAY_CONST_S0="0.523e-9" *)
(* DELAY_CONST_S1="0.558e-9" *)
(* DELAY_CONST_S2="0.226e-9" *)
(* DELAY_CONST_DI0="0.486e-9" *)
(* DELAY_CONST_DI1="0.471e-9" *)
output wire O2;
(* DELAY_CONST_CYINIT="0.657e-9" *)
(* DELAY_CONST_CIN="0.329e-9" *)
(* DELAY_CONST_S0="0.582e-9" *)
(* DELAY_CONST_S1="0.618e-9" *)
(* DELAY_CONST_S2="0.330e-9" *)
(* DELAY_CONST_S3="0.227e-9" *)
(* DELAY_CONST_DI0="0.545e-9" *)
(* DELAY_CONST_DI1="0.532e-9" *)
(* DELAY_CONST_DI2="0.372e-9" *)
output wire O3;
(* DELAY_CONST_CYINIT="0.578e-9" *)
(* DELAY_CONST_CIN="0.293e-9" *)
(* DELAY_CONST_S0="0.340e-9" *)
(* DELAY_CONST_DI0="0.329e-9" *)
output wire CO_FABRIC0;
(* DELAY_CONST_CYINIT="0.529e-9" *)
(* DELAY_CONST_CIN="0.178e-9" *)
(* DELAY_CONST_S0="0.433e-9" *)
(* DELAY_CONST_S1="0.469e-9" *)
(* DELAY_CONST_DI0="0.396e-9" *)
(* DELAY_CONST_DI1="0.376e-9" *)
output wire CO_FABRIC1;
(* DELAY_CONST_CYINIT="0.617e-9" *)
(* DELAY_CONST_CIN="0.250e-9" *)
(* DELAY_CONST_S0="0.512e-9" *)
(* DELAY_CONST_S1="0.548e-9" *)
(* DELAY_CONST_S2="0.292e-9" *)
(* DELAY_CONST_DI0="0.474e-9" *)
(* DELAY_CONST_DI1="0.459e-9" *)
(* DELAY_CONST_DI2="0.289e-9" *)
output wire CO_FABRIC2;
(* DELAY_CONST_CYINIT="0.580e-9" *)
(* DELAY_CONST_CIN="0.114e-9" *)
(* DELAY_CONST_S0="0.508e-9" *)
(* DELAY_CONST_S1="0.528e-9" *)
(* DELAY_CONST_S2="0.376e-9" *)
(* DELAY_CONST_S3="0.380e-9" *)
(* DELAY_CONST_DI0="0.456e-9" *)
(* DELAY_CONST_DI1="0.443e-9" *)
(* DELAY_CONST_DI2="0.324e-9" *)
(* DELAY_CONST_DI3="0.327e-9" *)
output wire CO_FABRIC3;
(* DELAY_CONST_CYINIT="0.580e-9" *)
(* DELAY_CONST_CIN="0.114e-9" *)
(* DELAY_CONST_S0="0.508e-9" *)
(* DELAY_CONST_S1="0.528e-9" *)
(* DELAY_CONST_S2="0.376e-9" *)
(* DELAY_CONST_S3="0.380e-9" *)
(* DELAY_CONST_DI0="0.456e-9" *)
(* DELAY_CONST_DI1="0.443e-9" *)
(* DELAY_CONST_DI2="0.324e-9" *)
(* DELAY_CONST_DI3="0.327e-9" *)
output wire CO_CHAIN;
input wire DI0, DI1, DI2, DI3;
input wire S0, S1, S2, S3;
input wire CYINIT;
input wire CIN;
wire CI0;
wire CI1;
wire CI2;
wire CI3;
wire CI4;
assign CI0 = (CYINIT & CYINIT_AX) | CYINIT_C1 | (CIN & (!CYINIT_AX && !CYINIT_C0 && !CYINIT_C1));
assign CI1 = S0 ? CI0 : DI0;
assign CI2 = S1 ? CI1 : DI1;
assign CI3 = S2 ? CI2 : DI2;
assign CI4 = S3 ? CI3 : DI3;
assign CO_FABRIC0 = CI1;
assign CO_FABRIC1 = CI2;
assign CO_FABRIC2 = CI3;
assign CO_FABRIC3 = CI4;
assign O0 = CI0 ^ S0;
assign O1 = CI1 ^ S1;
assign O2 = CI2 ^ S2;
assign O3 = CI3 ^ S3;
assign CO_CHAIN = CO_FABRIC3;
endmodule
Physical Block XML¶
<?xml version='1.0' encoding='utf-8'?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt CARRY4_VPR" name="CARRY4_VPR" num_pb="1">
<input name="CIN" num_pins="1"/>
<output name="CO_CHAIN" num_pins="1"/>
<output name="CO_FABRIC0" num_pins="1"/>
<output name="CO_FABRIC1" num_pins="1"/>
<output name="CO_FABRIC2" num_pins="1"/>
<output name="CO_FABRIC3" num_pins="1"/>
<input name="CYINIT" num_pins="1"/>
<input name="DI0" num_pins="1"/>
<input name="DI1" num_pins="1"/>
<input name="DI2" num_pins="1"/>
<input name="DI3" num_pins="1"/>
<output name="O0" num_pins="1"/>
<output name="O1" num_pins="1"/>
<output name="O2" num_pins="1"/>
<output name="O3" num_pins="1"/>
<input name="S0" num_pins="1"/>
<input name="S1" num_pins="1"/>
<input name="S2" num_pins="1"/>
<input name="S3" num_pins="1"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="DI1" max="{iopath_DI1_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="DI2" max="{iopath_DI2_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="DI3" max="{iopath_DI3_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="S0" max="{iopath_S0_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="S1" max="{iopath_S1_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="S2" max="{iopath_S2_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="S3" max="{iopath_S3_CO3}" out_port="CO_CHAIN"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO0}" out_port="CO_FABRIC0"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO0}" out_port="CO_FABRIC0"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO0}" out_port="CO_FABRIC0"/>
<delay_constant in_port="S0" max="{iopath_S0_CO0}" out_port="CO_FABRIC0"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="DI1" max="{iopath_DI1_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="S0" max="{iopath_S0_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="S1" max="{iopath_S1_CO1}" out_port="CO_FABRIC1"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="DI1" max="{iopath_DI1_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="DI2" max="{iopath_DI2_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="S0" max="{iopath_S0_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="S1" max="{iopath_S1_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="S2" max="{iopath_S2_CO2}" out_port="CO_FABRIC2"/>
<delay_constant in_port="CIN" max="{iopath_CIN_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="DI0" max="{iopath_DI0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="DI1" max="{iopath_DI0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="DI2" max="{iopath_DI0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="DI3" max="{iopath_DI0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="S0" max="{iopath_S0_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="S1" max="{iopath_S1_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="S2" max="{iopath_S2_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="S3" max="{iopath_S3_CO3}" out_port="CO_FABRIC3"/>
<delay_constant in_port="CIN" max="{iopath_CIN_O0}" out_port="O0"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_O0}" out_port="O0"/>
<delay_constant in_port="S0" max="{iopath_S0_O0}" out_port="O0"/>
<delay_constant in_port="CIN" max="{iopath_CIN_O1}" out_port="O1"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_O1}" out_port="O1"/>
<delay_constant in_port="DI0" max="{iopath_DI0_O1}" out_port="O1"/>
<delay_constant in_port="S0" max="{iopath_S0_O1}" out_port="O1"/>
<delay_constant in_port="S1" max="{iopath_S1_O1}" out_port="O1"/>
<delay_constant in_port="CIN" max="{iopath_CIN_O2}" out_port="O2"/>
<delay_constant in_port="CYINIT" max="{iopath_CYINIT_O2}" out_port="O2"/>
<delay_constant in_port="DI0" max="{iopath_DI0_O2}" out_port="O2"/>
<delay_constant in_port="DI1" max="{iopath_DI1_O2}" out_port="O2"/>
<delay_constant in_port="S0" max="{iopath_S0_O2}" out_port="O2"/>
<delay_constant in_port="S1" max="{iopath_S1_O2}" out_port="O2"/>
<delay_constant in_port="S2" max="{iopath_S2_O2}" out_port="O2"/>
<delay_constant in_port="CIN" max="{iopath_CIN_O3}" out_port="O3"/>
<delay_constant in_port="CYINIT" max="{iopath_CIN_O3}" out_port="O3"/>
<delay_constant in_port="DI0" max="{iopath_DI0_O3}" out_port="O3"/>
<delay_constant in_port="DI1" max="{iopath_DI1_O3}" out_port="O3"/>
<delay_constant in_port="DI2" max="{iopath_DI2_O3}" out_port="O3"/>
<delay_constant in_port="S0" max="{iopath_S0_O3}" out_port="O3"/>
<delay_constant in_port="S1" max="{iopath_S1_O3}" out_port="O3"/>
<delay_constant in_port="S2" max="{iopath_S2_O3}" out_port="O3"/>
<delay_constant in_port="S3" max="{iopath_S3_O3}" out_port="O3"/>
<metadata>
<meta name="fasm_params">
PRECYINIT.C0 = CYINIT_C0
PRECYINIT.C1 = CYINIT_C1
</meta>
<meta name="type">bel</meta>
<meta name="subtype">blackbox</meta>
</metadata>
</pb_type>
Model XML¶
<models xmlns:xi="http://www.w3.org/2001/XInclude">
<model name="CARRY4_VPR">
<input_ports>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 CO_FABRIC0 O3 O2 O1 O0" name="CIN"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 CO_FABRIC0 O3 O2 O1 O0" name="CYINIT"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 CO_FABRIC0 O3 O2 O1" name="DI0"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 O3 O2" name="DI1"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 O3" name="DI2"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3" name="DI3"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 CO_FABRIC0 O3 O2 O1 O0" name="S0"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 CO_FABRIC1 O3 O2 O1" name="S1"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 CO_FABRIC2 O3 O2" name="S2"/>
<port combinational_sink_ports="CO_CHAIN CO_FABRIC3 O3" name="S3"/>
</input_ports>
<output_ports>
<port name="CO_CHAIN"/>
<port name="CO_FABRIC0"/>
<port name="CO_FABRIC1"/>
<port name="CO_FABRIC2"/>
<port name="CO_FABRIC3"/>
<port name="O0"/>
<port name="O1"/>
<port name="O2"/>
<port name="O3"/>
</output_ports>
</model>
</models>