symbiflow-arch-defs
Table Of Contents
symbiflow-arch-defs
Table Of Contents

LUT4

Component Diagram

`default_nettype none module LUT4(input A, B, C, D, output Z); parameter [15:0] INIT = 16'h0000; wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0]; wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0]; assign Z = A ? s1[1] : s1[0]; endmodule

Internal Diagram

/home/docs/checkouts/readthedocs.org/user_builds/rw1nkler-symbiflow-arch-defs/checkouts/latest/ecp5/primitives/slice/LUT4/LUT4.sim.v

Verilog File

`default_nettype none
module LUT4(input A, B, C, D, output Z);
    parameter [15:0] INIT = 16'h0000;
    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
    assign Z =      A ?          s1[1] :         s1[0];
endmodule

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