ologice3¶
Physical Block XML¶
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="OLOGICE3" num_pb="1">
<input name="CLK" num_pins="1"/>
<input name="CLKB" num_pins="1"/>
<input name="CLKDIV" num_pins="1"/>
<input name="CLKDIVB" num_pins="1"/>
<input name="CLKDIVF" num_pins="1"/>
<input name="CLKDIVFB" num_pins="1"/>
<input name="D1" num_pins="1"/>
<input name="D2" num_pins="1"/>
<input name="D3" num_pins="1"/>
<input name="D4" num_pins="1"/>
<input name="D5" num_pins="1"/>
<input name="D6" num_pins="1"/>
<input name="D7" num_pins="1"/>
<input name="D8" num_pins="1"/>
<output name="IOCLKGLITCH" num_pins="1"/>
<input name="OCE" num_pins="1"/>
<output name="OFB" num_pins="1"/>
<output name="OQ" num_pins="1"/>
<output name="SHIFTOUT1" num_pins="1"/>
<output name="SHIFTOUT2" num_pins="1"/>
<input name="SR" num_pins="1"/>
<input name="T1" num_pins="1"/>
<input name="T2" num_pins="1"/>
<input name="T3" num_pins="1"/>
<input name="T4" num_pins="1"/>
<input name="TBYTEIN" num_pins="1"/>
<output name="TBYTEOUT" num_pins="1"/>
<input name="TCE" num_pins="1"/>
<output name="TFB" num_pins="1"/>
<output name="TQ" num_pins="1"/>
<input name="SHIFTIN1" num_pins="1"/>
<input name="SHIFTIN2" num_pins="1"/>
<!-- OLOGIC (ODDR/TDDR) or passthrough -->
<mode name="OLOGIC">
<!-- ODDR for T or passthrough -->
<pb_type name="OLOGIC_TFF" num_pb="1">
<input name="TCE" num_pins="1"/>
<input name="T1" num_pins="1"/>
<input name="T2" num_pins="1"/>
<input name="SR" num_pins="1"/>
<input name="CLK" num_pins="1"/>
<output name="TQ" num_pins="1"/>
<output name="TFB" num_pins="1"/>
<mode name="PASSTHROUGH">
<interconnect>
<direct name="T1_to_TQ" input="OLOGIC_TFF.T1" output="OLOGIC_TFF.TQ">
<metadata>
<meta name="fasm_mux">
OLOGIC_TFF.T1 : ZINV_T1,OSERDES.DATA_RATE_TQ.BUF
</meta>
</metadata>
</direct>
</interconnect>
</mode>
<mode name="T_INV">
<pb_type name="T_INV" blif_model=".subckt T_INV" num_pb="1">
<input name="TI" num_pins="1"/>
<output name="TO" num_pins="1"/>
<delay_constant in_port="TI" out_port="TO" max="1e-12"/>
<metadata>
<meta name="fasm_features">
OSERDES.DATA_RATE_TQ.BUF
</meta>
</metadata>
</pb_type>
<interconnect>
<direct name="TI" input="OLOGIC_TFF.T1" output="T_INV.TI"/>
<direct name="TO" input="T_INV.TO" output="OLOGIC_TFF.TQ"/>
</interconnect>
</mode>
<mode name="ODDR_TQ">
<pb_type name="ODDR_TQ" blif_model=".subckt ODDR_VPR" num_pb="1">
<clock name="CK" num_pins="1"/>
<input name="CE" num_pins="1"/>
<input name="SR" num_pins="1"/>
<input name="D1" num_pins="1"/>
<input name="D2" num_pins="1"/>
<output name="Q" num_pins="1"/>
<T_setup port="CE" clock="CK" value="{setup_CK_TCE}"/>
<T_hold port="CE" clock="CK" value="{hold_CK_TCE}"/>
<T_setup port="D1" clock="CK" value="{setup_CK_D1}"/>
<T_hold port="D1" clock="CK" value="{hold_CK_D1}"/>
<T_setup port="D2" clock="CK" value="{setup_CK_D2}"/>
<T_hold port="D2" clock="CK" value="{hold_CK_D2}"/>
<T_clock_to_Q port="Q" clock="CK" max="{iopath_CLK_Q}"/>
<metadata>
<meta name="fasm_features">
OSERDES.DATA_RATE_TQ.DDR
</meta>
<meta name="fasm_params">
ZINV_CLK = ZINV_CLK
ZINV_T1 = ZINV_D1
ZINV_T2 = ZINV_D2
OSERDES.TSRTYPE.SYNC = SRTYPE_SYNC
ODDR.DDR_CLK_EDGE.SAME_EDGE = SAME_EDGE
ZINIT_TQ = ZINIT_Q
ZSRVAL_TQ = ZSRVAL_Q
</meta>
</metadata>
</pb_type>
<interconnect>
<direct name="OLOGIC_TFF.CLK_to_ODDR.CK" input="OLOGIC_TFF.CLK" output="ODDR_TQ.CK"/>
<direct name="OLOGIC_TFF.SR_to_ODDR.SR" input="OLOGIC_TFF.SR" output="ODDR_TQ.SR"/>
<direct name="OLOGIC_TFF.TCE_to_ODDR.CE" input="OLOGIC_TFF.TCE" output="ODDR_TQ.CE"/>
<direct name="OLOGIC_TFF.T1_to_ODDR.D1" input="OLOGIC_TFF.T1" output="ODDR_TQ.D1"/>
<direct name="OLOGIC_TFF.T2_to_ODDR.D2" input="OLOGIC_TFF.T2" output="ODDR_TQ.D2"/>
<direct name="ODDR.Q_to_OLOGIC_TFF.TQ" input="ODDR_TQ.Q" output="OLOGIC_TFF.TQ"/>
</interconnect>
</mode>
</pb_type>
<!-- ODDR for D or passthrough -->
<pb_type name="OLOGIC_OFF" num_pb="1">
<input name="OCE" num_pins="1"/>
<input name="D1" num_pins="1"/>
<input name="D2" num_pins="1"/>
<input name="SR" num_pins="1"/>
<input name="CLK" num_pins="1"/>
<output name="OQ" num_pins="1"/>
<output name="OFB" num_pins="1"/>
<mode name="PASSTHROUGH">
<interconnect>
<direct name="D1_to_OQ" input="OLOGIC_OFF.D1" output="OLOGIC_OFF.OQ">
<metadata>
<meta name="fasm_mux">
OLOGIC_OFF.D1 : OMUX.D1,OQUSED
</meta>
</metadata>
</direct>
</interconnect>
</mode>
<mode name="ODDR_OQ">
<pb_type name="ODDR_OQ" blif_model=".subckt ODDR_VPR" num_pb="1">
<clock name="CK" num_pins="1"/>
<input name="CE" num_pins="1"/>
<input name="SR" num_pins="1"/>
<input name="D1" num_pins="1"/>
<input name="D2" num_pins="1"/>
<output name="Q" num_pins="1"/>
<T_setup port="CE" clock="CK" value="{setup_CK_OCE}"/>
<T_hold port="CE" clock="CK" value="{hold_CK_OCE}"/>
<T_setup port="D1" clock="CK" value="{setup_CK_D1}"/>
<T_hold port="D1" clock="CK" value="{hold_CK_D1}"/>
<T_setup port="D2" clock="CK" value="{setup_CK_D2}"/>
<T_hold port="D2" clock="CK" value="{hold_CK_D2}"/>
<T_clock_to_Q port="Q" clock="CK" max="{iopath_CLK_Q}"/>
<metadata>
<meta name="fasm_features">
OQUSED
OSERDES.DATA_RATE_OQ.DDR
</meta>
<meta name="fasm_params">
ZINV_CLK = ZINV_CLK
IS_D1_INVERTED = INV_D1
IS_D2_INVERTED = INV_D2
OSERDES.SRTYPE.SYNC = SRTYPE_SYNC
ODDR.DDR_CLK_EDGE.SAME_EDGE = SAME_EDGE
ZINIT_OQ = ZINIT_Q
ZSRVAL_OQ = ZSRVAL_Q
</meta>
</metadata>
</pb_type>
<interconnect>
<direct name="OLOGIC_OFF.CLK_to_ODDR.CK" input="OLOGIC_OFF.CLK" output="ODDR_OQ.CK"/>
<direct name="OLOGIC_OFF.SR_to_ODDR.SR" input="OLOGIC_OFF.SR" output="ODDR_OQ.SR"/>
<direct name="OLOGIC_OFF.OCE_to_ODDR.CE" input="OLOGIC_OFF.OCE" output="ODDR_OQ.CE"/>
<direct name="OLOGIC_OFF.D1_to_ODDR.D1" input="OLOGIC_OFF.D1" output="ODDR_OQ.D1"/>
<direct name="OLOGIC_OFF.D2_to_ODDR.D2" input="OLOGIC_OFF.D2" output="ODDR_OQ.D2"/>
<direct name="ODDR.Q_to_OLOGIC_OFF.OQ" input="ODDR_OQ.Q" output="OLOGIC_OFF.OQ"/>
</interconnect>
</mode>
</pb_type>
<interconnect>
<direct name="OLOGICE3.TCE_to_OLOGIC_TFF.TCE" input="OLOGICE3.TCE" output="OLOGIC_TFF.TCE"/>
<direct name="OLOGICE3.T1_to_OLOGIC_TFF.T1" input="OLOGICE3.T1" output="OLOGIC_TFF.T1"/>
<direct name="OLOGICE3.T2_to_OLOGIC_TFF.T2" input="OLOGICE3.T2" output="OLOGIC_TFF.T2"/>
<direct name="OLOGICE3.OCE_to_OLOGIC_OFF.OCE" input="OLOGICE3.OCE" output="OLOGIC_OFF.OCE"/>
<direct name="OLOGICE3.D1_to_OLOGIC_OFF.D1" input="OLOGICE3.D1" output="OLOGIC_OFF.D1"/>
<direct name="OLOGICE3.D2_to_OLOGIC_OFF.D2" input="OLOGICE3.D2" output="OLOGIC_OFF.D2"/>
<direct name="OLOGICE3.SR_to_OLOGIC_TFF.SR" input="OLOGICE3.SR" output="OLOGIC_TFF.SR"/>
<direct name="OLOGICE3.CLK_to_OLOGIC_TFF.CLK" input="OLOGICE3.CLK" output="OLOGIC_TFF.CLK"/>
<direct name="OLOGICE3.SR_to_OLOGIC_OFF.SR" input="OLOGICE3.SR" output="OLOGIC_OFF.SR"/>
<direct name="OLOGICE3.CLK_to_OLOGIC_OFF.CLK" input="OLOGICE3.CLK" output="OLOGIC_OFF.CLK"/>
<direct name="OLOGIC_TFF.TQ_to_OLOGICE3.TQ" input="OLOGIC_TFF.TQ" output="OLOGICE3.TQ"/>
<direct name="OLOGIC_TFF.TFB_to_OLOGICE3.TFB" input="OLOGIC_TFF.TFB" output="OLOGICE3.TFB"/>
<direct name="OLOGIC_OFF.OQ_to_OLOGICE3.OQ" input="OLOGIC_OFF.OQ" output="OLOGICE3.OQ"/>
<direct name="OLOGIC_OFF.OFB_to_OLOGICE3.OFB" input="OLOGIC_OFF.OFB" output="OLOGICE3.OFB"/>
</interconnect>
</mode>
<mode name="OSERDES">
<pb_type name="OSERDESE2" blif_model=".subckt OSERDESE2_VPR" num_pb="1">
<clock name="CLK" num_pins="1"/>
<clock name="CLKDIV" num_pins="1"/>
<input name="D1" num_pins="1"/>
<input name="D2" num_pins="1"/>
<input name="D3" num_pins="1"/>
<input name="D4" num_pins="1"/>
<input name="D5" num_pins="1"/>
<input name="D6" num_pins="1"/>
<input name="D7" num_pins="1"/>
<input name="D8" num_pins="1"/>
<output name="IOCLKGLITCH" num_pins="1"/>
<input name="OCE" num_pins="1"/>
<output name="OFB" num_pins="1"/>
<output name="OQ" num_pins="1"/>
<output name="SHIFTOUT1" num_pins="1"/>
<output name="SHIFTOUT2" num_pins="1"/>
<input name="RST" num_pins="1"/>
<input name="T1" num_pins="1"/>
<input name="T2" num_pins="1"/>
<input name="T3" num_pins="1"/>
<input name="T4" num_pins="1"/>
<input name="TBYTEIN" num_pins="1"/>
<output name="TBYTEOUT" num_pins="1"/>
<input name="TCE" num_pins="1"/>
<output name="TFB" num_pins="1"/>
<output name="TQ" num_pins="1"/>
<input name="SHIFTIN1" num_pins="1"/>
<input name="SHIFTIN2" num_pins="1"/>
<T_clock_to_Q max="{iopath_CLK_OFB}" clock="CLK" port="OFB" />
<T_clock_to_Q max="{iopath_CLK_OQ}" clock="CLK" port="OQ" />
<T_clock_to_Q max="{iopath_CLK_TFB}" clock="CLK" port="TFB" />
<T_clock_to_Q max="{iopath_CLK_TQ}" clock="CLK" port="TQ" />
<T_clock_to_Q max="{iopath_CLKDIV_IOCLKGLITCH}" clock="CLKDIV" port="IOCLKGLITCH" />
<T_setup value="{setup_CLKDIV_D1}" clock="CLKDIV" port="D1" />
<T_hold value="{hold_CLKDIV_D1}" clock="CLKDIV" port="D1" />
<T_setup value="{setup_CLKDIV_D2}" clock="CLKDIV" port="D2" />
<T_hold value="{hold_CLKDIV_D2}" clock="CLKDIV" port="D2" />
<T_setup value="{setup_CLKDIV_D3}" clock="CLKDIV" port="D3" />
<T_hold value="{hold_CLKDIV_D3}" clock="CLKDIV" port="D3" />
<T_setup value="{setup_CLKDIV_D4}" clock="CLKDIV" port="D4" />
<T_hold value="{hold_CLKDIV_D4}" clock="CLKDIV" port="D4" />
<T_setup value="{setup_CLKDIV_D5}" clock="CLKDIV" port="D5" />
<T_hold value="{hold_CLKDIV_D5}" clock="CLKDIV" port="D5" />
<T_setup value="{setup_CLKDIV_D6}" clock="CLKDIV" port="D6" />
<T_hold value="{hold_CLKDIV_D6}" clock="CLKDIV" port="D6" />
<T_setup value="{setup_CLKDIV_D7}" clock="CLKDIV" port="D7" />
<T_hold value="{hold_CLKDIV_D7}" clock="CLKDIV" port="D7" />
<T_setup value="{setup_CLKDIV_D8}" clock="CLKDIV" port="D8" />
<T_hold value="{hold_CLKDIV_D8}" clock="CLKDIV" port="D8" />
<!-- Unclear what this is for, but VPR wants it... -->
<T_clock_to_Q max="0.0" clock="CLKDIV" port="T1" />
<T_setup value="{setup_CLKDIV_T1}" clock="CLKDIV" port="T1" />
<T_hold value="{hold_CLKDIV_T1}" clock="CLKDIV" port="T1" />
<T_setup value="{setup_CLKDIV_T2}" clock="CLKDIV" port="T2" />
<T_hold value="{hold_CLKDIV_T2}" clock="CLKDIV" port="T2" />
<T_setup value="{setup_CLKDIV_T3}" clock="CLKDIV" port="T3" />
<T_hold value="{hold_CLKDIV_T3}" clock="CLKDIV" port="T3" />
<T_setup value="{setup_CLKDIV_T4}" clock="CLKDIV" port="T4" />
<T_hold value="{hold_CLKDIV_T4}" clock="CLKDIV" port="T4" />
<T_setup value="{setup_CLK_OCE}" clock="CLK" port="OCE" />
<T_hold value="{hold_CLK_OCE}" clock="CLK" port="OCE" />
<T_setup value="{setup_CLK_TCE}" clock="CLK" port="TCE" />
<T_hold value="{hold_CLK_TCE}" clock="CLK" port="TCE" />
<T_setup value="{setup_CLKDIV_RST}" clock="CLKDIV" port="RST" />
<T_hold value="{hold_CLKDIV_RST}" clock="CLKDIV" port="RST" />
<delay_constant max="{iopath_T1_TBYTEOUT}" in_port="T1" out_port="TBYTEOUT" />
<metadata>
<meta name="fasm_features">
OSERDES.IN_USE
OSERDES.SRTYPE.SYNC
OSERDES.TSRTYPE.SYNC
ODDR.DDR_CLK_EDGE.SAME_EDGE
OQUSED
</meta>
<meta name="fasm_params">
OSERDES.SERDES_MODE.SLAVE = SERDES_MODE_SLAVE
OSERDES.TRISTATE_WIDTH.W4 = TRISTATE_WIDTH_W4
OSERDES.DATA_RATE_OQ.DDR = DATA_RATE_OQ_DDR
OSERDES.DATA_RATE_OQ.SDR = DATA_RATE_OQ_SDR
OSERDES.DATA_RATE_TQ.BUF = DATA_RATE_TQ_BUF
OSERDES.DATA_RATE_TQ.DDR = DATA_RATE_TQ_DDR
OSERDES.DATA_RATE_TQ.SDR = DATA_RATE_TQ_SDR
OSERDES.DATA_WIDTH.DDR.W6_8 = DATA_WIDTH_DDR_W6_8
OSERDES.DATA_WIDTH.SDR.W2_4_5_6 = DATA_WIDTH_SDR_W2_4_5_6
OSERDES.DATA_WIDTH.W2 = DATA_WIDTH_W2
OSERDES.DATA_WIDTH.W3 = DATA_WIDTH_W3
OSERDES.DATA_WIDTH.W4 = DATA_WIDTH_W4
OSERDES.DATA_WIDTH.W5 = DATA_WIDTH_W5
OSERDES.DATA_WIDTH.W6 = DATA_WIDTH_W6
OSERDES.DATA_WIDTH.W7 = DATA_WIDTH_W7
OSERDES.DATA_WIDTH.W8 = DATA_WIDTH_W8
ZINIT_OQ = ZINIT_OQ
ZINIT_TQ = ZINIT_TQ
ZINV_CLK = ZINV_CLK
ZSRVAL_OQ = ZSRVAL_OQ
ZSRVAL_TQ = ZSRVAL_TQ
ZINV_T1 = ZINV_T1
ZINV_T2 = ZINV_T2
ZINV_T3 = ZINV_T3
ZINV_T4 = ZINV_T4
IS_D1_INVERTED = IS_D1_INVERTED
IS_D2_INVERTED = IS_D2_INVERTED
IS_D3_INVERTED = IS_D3_INVERTED
IS_D4_INVERTED = IS_D4_INVERTED
IS_D5_INVERTED = IS_D5_INVERTED
IS_D6_INVERTED = IS_D6_INVERTED
IS_D7_INVERTED = IS_D7_INVERTED
IS_D8_INVERTED = IS_D8_INVERTED
</meta>
</metadata>
</pb_type>
<!-- This is a model of the inverter for T signal. It is used when the T
net bypasses the OSERDES and is connected to const0. In that case
the route actually goes to const1 and this inverter is used.
Note that there are no fasm features emitted. That's because not
emitting the ZINV_T1 feature enables the inversion.
When the T signal is connected to the OSERDES then the inversion is
controlled by its parameter. -->
<pb_type name="T_INV" blif_model=".subckt T_INV" num_pb="1">
<input name="TI" num_pins="1"/>
<output name="TO" num_pins="1"/>
<delay_constant in_port="TI" out_port="TO" max="1e-12"/>
</pb_type>
<interconnect>
<direct name="CLK" input="OLOGICE3.CLK" output="OSERDESE2.CLK" />
<direct name="CLKDIV" input="OLOGICE3.CLKDIV" output="OSERDESE2.CLKDIV" />
<direct name="D1" input="OLOGICE3.D1" output="OSERDESE2.D1" />
<direct name="D2" input="OLOGICE3.D2" output="OSERDESE2.D2" />
<direct name="D3" input="OLOGICE3.D3" output="OSERDESE2.D3" />
<direct name="D4" input="OLOGICE3.D4" output="OSERDESE2.D4" />
<direct name="D5" input="OLOGICE3.D5" output="OSERDESE2.D5" />
<direct name="D6" input="OLOGICE3.D6" output="OSERDESE2.D6" />
<direct name="D7" input="OLOGICE3.D7" output="OSERDESE2.D7" />
<direct name="D8" input="OLOGICE3.D8" output="OSERDESE2.D8" />
<direct name="IOCLKGLITCH" input="OSERDESE2.IOCLKGLITCH" output="OLOGICE3.IOCLKGLITCH" />
<direct name="OCE" input="OLOGICE3.OCE" output="OSERDESE2.OCE" />
<direct name="OFB" input="OSERDESE2.OFB" output="OLOGICE3.OFB" />
<direct name="OQ" input="OSERDESE2.OQ" output="OLOGICE3.OQ" />
<direct name="SHIFTOUT1" input="OSERDESE2.SHIFTOUT1" output="OLOGICE3.SHIFTOUT1" />
<direct name="SHIFTOUT2" input="OSERDESE2.SHIFTOUT2" output="OLOGICE3.SHIFTOUT2" />
<direct name="SR" input="OLOGICE3.SR" output="OSERDESE2.RST" />
<direct name="T1" input="OLOGICE3.T1" output="OSERDESE2.T1" />
<direct name="T2" input="OLOGICE3.T2" output="OSERDESE2.T2" />
<direct name="T3" input="OLOGICE3.T3" output="OSERDESE2.T3" />
<direct name="T4" input="OLOGICE3.T4" output="OSERDESE2.T4" />
<direct name="TBYTEIN" input="OLOGICE3.TBYTEIN" output="OSERDESE2.TBYTEIN" />
<direct name="TBYTEOUT" input="OSERDESE2.TBYTEOUT" output="OLOGICE3.TBYTEOUT" />
<direct name="TCE" input="OLOGICE3.TCE" output="OSERDESE2.TCE" />
<direct name="TFB" input="OSERDESE2.TFB" output="OLOGICE3.TFB" />
<direct name="SHIFTIN1" input="OLOGICE3.SHIFTIN1" output="OSERDESE2.SHIFTIN1" />
<direct name="SHIFTIN2" input="OLOGICE3.SHIFTIN2" output="OSERDESE2.SHIFTIN2" />
<!-- This is a routing mux that allows the T signal to bypass the OSERDES
when it is in "TQ BUF" mode. This is used when the T connection is
routed to const0, see the comment on the "T_INV" pb_type above.
When T is connected to const0 it is being actually routed to cons1
through the T_INV inverter and the T1 input pin. When it is connected
to the OSERDES it is routed to the TQ output of it. -->
<direct name="T1_to_T_INV.TI" input="OLOGICE3.T1" output="T_INV.TI"/>
<mux name="TQ" input="OSERDESE2.TQ T_INV.TO" output="OLOGICE3.TQ"/>
</interconnect>
</mode>
<!-- TODO
- other modes
- BELs
-->
</pb_type>
Model XML¶
<models xmlns:xi="http://www.w3.org/2001/XInclude">
<model name="OSERDESE2_VPR">
<input_ports>
<port is_clock="1" name="CLK"/>
<port is_clock="1" name="CLKDIV"/>
<port clock="CLKDIV" name="D1"/>
<port clock="CLKDIV" name="D2"/>
<port clock="CLKDIV" name="D3"/>
<port clock="CLKDIV" name="D4"/>
<port clock="CLKDIV" name="D5"/>
<port clock="CLKDIV" name="D6"/>
<port clock="CLKDIV" name="D7"/>
<port clock="CLKDIV" name="D8"/>
<port clock="CLK" name="OCE"/>
<port clock="CLKDIV" name="RST"/>
<port clock="CLKDIV" combinational_sink_ports="TBYTEOUT" name="T1"/>
<port clock="CLKDIV" name="T2"/>
<port clock="CLKDIV" name="T3"/>
<port clock="CLKDIV" name="T4"/>
<port name="TBYTEIN"/>
<port clock="CLK" name="TCE"/>
<port name="SHIFTIN1"/>
<port name="SHIFTIN2"/>
</input_ports>
<output_ports>
<port clock="CLKDIV" name="IOCLKGLITCH"/>
<port clock="CLK" name="OFB"/>
<port clock="CLK" name="OQ"/>
<port name="SHIFTOUT1"/>
<port name="SHIFTOUT2"/>
<port name="TBYTEOUT"/>
<port clock="CLK" name="TFB"/>
<port clock="CLK" name="TQ"/>
</output_ports>
</model>
<model name="ODDR_VPR">
<input_ports>
<port name="CK" is_clock="1"/>
<port name="CE" clock="CK"/>
<port name="SR"/>
<port name="D1" clock="CK"/>
<port name="D2" clock="CK"/>
</input_ports>
<output_ports>
<port name="Q" clock="CK"/>
</output_ports>
</model>
<model name="T_INV">
<input_ports>
<port name="TI" combinational_sink_ports="TO"/>
</input_ports>
<output_ports>
<port name="TO"/>
</output_ports>
</model>
</models>