sb_carry¶

Component Diagram¶

Internal Diagram¶

/home/docs/checkouts/readthedocs.org/user_builds/rw1nkler-symbiflow-arch-defs/checkouts/latest/ice40/primitives/sb_carry/sb_carry.sim.v

Verilog File¶

module SB_CARRY (CO, I0, I1, CI);
	output wire CO;
	input wire I0;
	input wire I1;
	input wire CI;

	assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule

Physical Block XML¶

<!-- set: ai sw=1 ts=1 sta et -->
<!-- Carry logic found in the ICE40 -->
<pb_type name="SB_CARRY" num_pb="1" blif_model=".subckt SB_CARRY">
 <input  name="I1" num_pins="1"/>
 <input  name="CI" num_pins="1"/>
 <input  name="I0" num_pins="1"/>
 <output name="CO" num_pins="1"/>
 <delay_constant max="10e-12" in_port="CI" out_port="CO"/>
 <delay_constant max="10e-12" in_port="I1" out_port="CO"/>
 <delay_constant max="10e-12" in_port="I0" out_port="CO"/>
 <metadata>
  <meta name="hlc_property">enable_carry</meta>
 </metadata>
</pb_type>

Model XML¶

<!-- set: ai sw=1 ts=1 sta et -->
<models>
 <model name="SB_CARRY">
  <input_ports>
   <port name="I0" combinational_sink_ports="CO" /> <!-- I1 -->
   <port name="I1" combinational_sink_ports="CO" /> <!-- I2 -->
   <port name="CI" combinational_sink_ports="CO" /> <!-- FCIN -->
  </input_ports>
  <output_ports>
   <port name="CO" /> <!-- FCOUT -->
  </output_ports>
 </model>
</models>