slicem¶
Physical Block XML¶
<!-- A diagram for the SLICEM is shown in;
7 Series FPGAs CLB User Guide UG474 (v1.8) September 27, 2016
-->
<pb_type name="SLICEM" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
<input name="DI" num_pins="1"/>
<input name="DX" num_pins="1"/>
<input name="D1" num_pins="1"/>
<input name="D2" num_pins="1"/>
<input name="D3" num_pins="1"/>
<input name="D4" num_pins="1"/>
<input name="D5" num_pins="1"/>
<input name="D6" num_pins="1"/>
<input name="CI" num_pins="1"/>
<input name="CX" num_pins="1"/>
<input name="C1" num_pins="1"/>
<input name="C2" num_pins="1"/>
<input name="C3" num_pins="1"/>
<input name="C4" num_pins="1"/>
<input name="C5" num_pins="1"/>
<input name="C6" num_pins="1"/>
<input name="BI" num_pins="1"/>
<input name="BX" num_pins="1"/>
<input name="B1" num_pins="1"/>
<input name="B2" num_pins="1"/>
<input name="B3" num_pins="1"/>
<input name="B4" num_pins="1"/>
<input name="B5" num_pins="1"/>
<input name="B6" num_pins="1"/>
<input name="AI" num_pins="1"/>
<input name="AX" num_pins="1"/>
<input name="A1" num_pins="1"/>
<input name="A2" num_pins="1"/>
<input name="A3" num_pins="1"/>
<input name="A4" num_pins="1"/>
<input name="A5" num_pins="1"/>
<input name="A6" num_pins="1"/>
<input name="SR" num_pins="1"/>
<input name="CE" num_pins="1"/>
<input name="WE" num_pins="1"/>
<clock name="CLK" num_pins="1"/>
<input name="CIN" num_pins="1"/>
<output name="COUT" num_pins="1"/>
<output name="DMUX" num_pins="1"/>
<output name="D" num_pins="1"/>
<output name="DQ" num_pins="1"/>
<output name="CMUX" num_pins="1"/>
<output name="C" num_pins="1"/>
<output name="CQ" num_pins="1"/>
<output name="BMUX" num_pins="1"/>
<output name="B" num_pins="1"/>
<output name="BQ" num_pins="1"/>
<output name="AMUX" num_pins="1"/>
<output name="A" num_pins="1"/>
<output name="AQ" num_pins="1"/>
<xi:include href="../common_slice/common_slice.pb_type.xml"/>
<pb_type name="SLICEM_MODES" num_pb="1">
<input name="DI" num_pins="1"/>
<input name="DX" num_pins="1"/>
<input name="D1" num_pins="1"/>
<input name="D2" num_pins="1"/>
<input name="D3" num_pins="1"/>
<input name="D4" num_pins="1"/>
<input name="D5" num_pins="1"/>
<input name="D6" num_pins="1"/>
<input name="CI" num_pins="1"/>
<input name="CX" num_pins="1"/>
<input name="C1" num_pins="1"/>
<input name="C2" num_pins="1"/>
<input name="C3" num_pins="1"/>
<input name="C4" num_pins="1"/>
<input name="C5" num_pins="1"/>
<input name="C6" num_pins="1"/>
<input name="BI" num_pins="1"/>
<input name="BX" num_pins="1"/>
<input name="B1" num_pins="1"/>
<input name="B2" num_pins="1"/>
<input name="B3" num_pins="1"/>
<input name="B4" num_pins="1"/>
<input name="B5" num_pins="1"/>
<input name="B6" num_pins="1"/>
<input name="AI" num_pins="1"/>
<input name="AX" num_pins="1"/>
<input name="A1" num_pins="1"/>
<input name="A2" num_pins="1"/>
<input name="A3" num_pins="1"/>
<input name="A4" num_pins="1"/>
<input name="A5" num_pins="1"/>
<input name="A6" num_pins="1"/>
<input name="WA7" num_pins="1"/>
<input name="WA8" num_pins="1"/>
<input name="CE" num_pins="1"/>
<input name="WE" num_pins="1"/>
<output name="DO6" num_pins="1"/>
<output name="DO5" num_pins="1"/>
<output name="CO6" num_pins="1"/>
<output name="CO5" num_pins="1"/>
<output name="BO6" num_pins="1"/>
<output name="BO5" num_pins="1"/>
<output name="AO6" num_pins="1"/>
<output name="AO5" num_pins="1"/>
<output name="F7AMUX_O" num_pins="1"/>
<output name="F7BMUX_O" num_pins="1"/>
<output name="F8MUX_O" num_pins="1"/>
<output name="AMC31" num_pins="1"/>
<clock name="CLK" num_pins="1"/>
<mode name="LUTs">
<xi:include href="../common_slice/common_lut_and_f78mux.pb_type.xml"/>
<interconnect>
<!-- Normal LUT input pins -->
<direct name="D1" input="SLICEM_MODES.D1" output="COMMON_LUT_AND_F78MUX.D1" />
<direct name="D2" input="SLICEM_MODES.D2" output="COMMON_LUT_AND_F78MUX.D2" />
<direct name="D3" input="SLICEM_MODES.D3" output="COMMON_LUT_AND_F78MUX.D3" />
<direct name="D4" input="SLICEM_MODES.D4" output="COMMON_LUT_AND_F78MUX.D4" />
<direct name="D5" input="SLICEM_MODES.D5" output="COMMON_LUT_AND_F78MUX.D5" />
<direct name="D6" input="SLICEM_MODES.D6" output="COMMON_LUT_AND_F78MUX.D6" />
<direct name="C1" input="SLICEM_MODES.C1" output="COMMON_LUT_AND_F78MUX.C1" />
<direct name="C2" input="SLICEM_MODES.C2" output="COMMON_LUT_AND_F78MUX.C2" />
<direct name="C3" input="SLICEM_MODES.C3" output="COMMON_LUT_AND_F78MUX.C3" />
<direct name="C4" input="SLICEM_MODES.C4" output="COMMON_LUT_AND_F78MUX.C4" />
<direct name="C5" input="SLICEM_MODES.C5" output="COMMON_LUT_AND_F78MUX.C5" />
<direct name="C6" input="SLICEM_MODES.C6" output="COMMON_LUT_AND_F78MUX.C6" />
<direct name="B1" input="SLICEM_MODES.B1" output="COMMON_LUT_AND_F78MUX.B1" />
<direct name="B2" input="SLICEM_MODES.B2" output="COMMON_LUT_AND_F78MUX.B2" />
<direct name="B3" input="SLICEM_MODES.B3" output="COMMON_LUT_AND_F78MUX.B3" />
<direct name="B4" input="SLICEM_MODES.B4" output="COMMON_LUT_AND_F78MUX.B4" />
<direct name="B5" input="SLICEM_MODES.B5" output="COMMON_LUT_AND_F78MUX.B5" />
<direct name="B6" input="SLICEM_MODES.B6" output="COMMON_LUT_AND_F78MUX.B6" />
<direct name="A1" input="SLICEM_MODES.A1" output="COMMON_LUT_AND_F78MUX.A1" />
<direct name="A2" input="SLICEM_MODES.A2" output="COMMON_LUT_AND_F78MUX.A2" />
<direct name="A3" input="SLICEM_MODES.A3" output="COMMON_LUT_AND_F78MUX.A3" />
<direct name="A4" input="SLICEM_MODES.A4" output="COMMON_LUT_AND_F78MUX.A4" />
<direct name="A5" input="SLICEM_MODES.A5" output="COMMON_LUT_AND_F78MUX.A5" />
<direct name="A6" input="SLICEM_MODES.A6" output="COMMON_LUT_AND_F78MUX.A6" />
<direct name="CX" input="SLICEM_MODES.CX" output="COMMON_LUT_AND_F78MUX.CX" />
<direct name="BX" input="SLICEM_MODES.BX" output="COMMON_LUT_AND_F78MUX.BX" />
<direct name="AX" input="SLICEM_MODES.AX" output="COMMON_LUT_AND_F78MUX.AX" />
<!-- COMMON_SLICE inputs -->
<direct name="DO6" input="COMMON_LUT_AND_F78MUX.DO6" output="SLICEM_MODES.DO6" />
<direct name="DO5" input="COMMON_LUT_AND_F78MUX.DO5" output="SLICEM_MODES.DO5" />
<direct name="CO6" input="COMMON_LUT_AND_F78MUX.CO6" output="SLICEM_MODES.CO6" />
<direct name="CO5" input="COMMON_LUT_AND_F78MUX.CO5" output="SLICEM_MODES.CO5" />
<direct name="BO6" input="COMMON_LUT_AND_F78MUX.BO6" output="SLICEM_MODES.BO6" />
<direct name="BO5" input="COMMON_LUT_AND_F78MUX.BO5" output="SLICEM_MODES.BO5" />
<direct name="AO6" input="COMMON_LUT_AND_F78MUX.AO6" output="SLICEM_MODES.AO6" />
<direct name="AO5" input="COMMON_LUT_AND_F78MUX.AO5" output="SLICEM_MODES.AO5" />
<direct name="F7AMUX_O" input="COMMON_LUT_AND_F78MUX.F7AMUX_O" output="SLICEM_MODES.F7AMUX_O" />
<direct name="F7BMUX_O" input="COMMON_LUT_AND_F78MUX.F7BMUX_O" output="SLICEM_MODES.F7BMUX_O" />
<direct name="F8MUX_O" input="COMMON_LUT_AND_F78MUX.F8MUX_O" output="SLICEM_MODES.F8MUX_O" />
</interconnect>
</mode>
<mode name="SRLs">
<!-- SRLs -->
<xi:include href="srl/a_srl.pb_type.xml"/>
<xi:include href="srl/b_srl.pb_type.xml"/>
<xi:include href="srl/c_srl.pb_type.xml"/>
<xi:include href="srl/d_srl.pb_type.xml"/>
<!-- F7AMUX, F7BMUX, F8MUX -->
<xi:include href="../common_slice/muxes/f7amux/f7amux.pb_type.xml"/>
<xi:include href="../common_slice/muxes/f7bmux/f7bmux.pb_type.xml"/>
<xi:include href="../common_slice/muxes/f8mux/f8mux.pb_type.xml"/>
<!-- WEMUX -->
<xi:include href="wemux.pb_type.xml"/>
<interconnect>
<!-- A SRL -->
<direct name="SLICEM_MODES.CLK_to_A_SRL.CLK" input="SLICEM_MODES.CLK" output="ASRL.CLK"/>
<direct name="WE_MUX_to_A_SRL.WE" input="WE_MUX.WE_OUT" output="ASRL.WE"/>
<direct name="SLICEM_MODES.A1_to_A_SRL.A1" input="SLICEM_MODES.A1" output="ASRL.A1"/>
<direct name="SLICEM_MODES.A2_to_A_SRL.A2" input="SLICEM_MODES.A2" output="ASRL.A2"/>
<direct name="SLICEM_MODES.A3_to_A_SRL.A3" input="SLICEM_MODES.A3" output="ASRL.A3"/>
<direct name="SLICEM_MODES.A4_to_A_SRL.A4" input="SLICEM_MODES.A4" output="ASRL.A4"/>
<direct name="SLICEM_MODES.A5_to_A_SRL.A5" input="SLICEM_MODES.A5" output="ASRL.A5"/>
<direct name="SLICEM_MODES.A6_to_A_SRL.A6" input="SLICEM_MODES.A6" output="ASRL.A6"/>
<direct name="SLICEM_MODES.AX_to_A_SRL.DI2" input="SLICEM_MODES.AX" output="ASRL.DI2"/>
<direct name="A_SRL.O5_to_SLICEM_MODES.AO5" input="ASRL.O5" output="SLICEM_MODES.AO5"/>
<direct name="A_SRL.O6_to_SLICEM_MODES.AO6" input="ASRL.O6" output="SLICEM_MODES.AO6"/>
<!-- B SRL -->
<direct name="SLICEM_MODES.CLK_to_B_SRL.CLK" input="SLICEM_MODES.CLK" output="BSRL.CLK"/>
<direct name="WE_MUX_to_B_SRL.WE" input="WE_MUX.WE_OUT" output="BSRL.WE"/>
<direct name="SLICEM_MODES.B1_to_B_SRL.A1" input="SLICEM_MODES.B1" output="BSRL.A1"/>
<direct name="SLICEM_MODES.B2_to_B_SRL.A2" input="SLICEM_MODES.B2" output="BSRL.A2"/>
<direct name="SLICEM_MODES.B3_to_B_SRL.A3" input="SLICEM_MODES.B3" output="BSRL.A3"/>
<direct name="SLICEM_MODES.B4_to_B_SRL.A4" input="SLICEM_MODES.B4" output="BSRL.A4"/>
<direct name="SLICEM_MODES.B5_to_B_SRL.A5" input="SLICEM_MODES.B5" output="BSRL.A5"/>
<direct name="SLICEM_MODES.B6_to_B_SRL.A6" input="SLICEM_MODES.B6" output="BSRL.A6"/>
<direct name="SLICEM_MODES.BX_to_B_SRL.DI2" input="SLICEM_MODES.BX" output="BSRL.DI2"/>
<direct name="B_SRL.O5_to_SLICEM_MODES.BO5" input="BSRL.O5" output="SLICEM_MODES.BO5"/>
<direct name="B_SRL.O6_to_SLICEM_MODES.BO6" input="BSRL.O6" output="SLICEM_MODES.BO6"/>
<!-- C SRL -->
<direct name="SLICEM_MODES.CLK_to_C_SRL.CLK" input="SLICEM_MODES.CLK" output="CSRL.CLK"/>
<direct name="WE_MUX_to_C_SRL.WE" input="WE_MUX.WE_OUT" output="CSRL.WE"/>
<direct name="SLICEM_MODES.C1_to_C_SRL.A1" input="SLICEM_MODES.C1" output="CSRL.A1"/>
<direct name="SLICEM_MODES.C2_to_C_SRL.A2" input="SLICEM_MODES.C2" output="CSRL.A2"/>
<direct name="SLICEM_MODES.C3_to_C_SRL.A3" input="SLICEM_MODES.C3" output="CSRL.A3"/>
<direct name="SLICEM_MODES.C4_to_C_SRL.A4" input="SLICEM_MODES.C4" output="CSRL.A4"/>
<direct name="SLICEM_MODES.C5_to_C_SRL.A5" input="SLICEM_MODES.C5" output="CSRL.A5"/>
<direct name="SLICEM_MODES.C6_to_C_SRL.A6" input="SLICEM_MODES.C6" output="CSRL.A6"/>
<direct name="SLICEM_MODES.CX_to_C_SRL.DI2" input="SLICEM_MODES.CX" output="CSRL.DI2"/>
<direct name="C_SRL.O5_to_SLICEM_MODES.CO5" input="CSRL.O5" output="SLICEM_MODES.CO5"/>
<direct name="C_SRL.O6_to_SLICEM_MODES.CO6" input="CSRL.O6" output="SLICEM_MODES.CO6"/>
<!-- D SRL -->
<direct name="SLICEM_MODES.CLK_to_D_SRL.CLK" input="SLICEM_MODES.CLK" output="DSRL.CLK"/>
<direct name="WE_MUX_to_D_SRL.WE" input="WE_MUX.WE_OUT" output="DSRL.WE"/>
<direct name="SLICEM_MODES.D1_to_D_SRL.A1" input="SLICEM_MODES.D1" output="DSRL.A1"/>
<direct name="SLICEM_MODES.D2_to_D_SRL.A2" input="SLICEM_MODES.D2" output="DSRL.A2"/>
<direct name="SLICEM_MODES.D3_to_D_SRL.A3" input="SLICEM_MODES.D3" output="DSRL.A3"/>
<direct name="SLICEM_MODES.D4_to_D_SRL.A4" input="SLICEM_MODES.D4" output="DSRL.A4"/>
<direct name="SLICEM_MODES.D5_to_D_SRL.A5" input="SLICEM_MODES.D5" output="DSRL.A5"/>
<direct name="SLICEM_MODES.D6_to_D_SRL.A6" input="SLICEM_MODES.D6" output="DSRL.A6"/>
<direct name="SLICEM_MODES.DI_to_D_SRL.DI1_SRL32" input="SLICEM_MODES.DI" output="DSRL.DI1_SRL32"/>
<direct name="SLICEM_MODES.DI_to_D_SRL.DI1_SRL16" input="SLICEM_MODES.DI" output="DSRL.DI1_SRL16"/>
<direct name="SLICEM_MODES.DX_to_D_SRL.DI2" input="SLICEM_MODES.DX" output="DSRL.DI2"/>
<direct name="D_SRL.O5_to_SLICEM_MODES.DO5" input="DSRL.O5" output="SLICEM_MODES.DO5"/>
<direct name="D_SRL.O6_to_SLICEM_MODES.DO6" input="DSRL.O6" output="SLICEM_MODES.DO6"/>
<!-- CE and WE -->
<direct name="SLICEM_MODES.CE_to_WE_MUX.CE" input="SLICEM_MODES.CE" output="WE_MUX.CE"/>
<direct name="SLICEM_MODES.WE_to_WE_MUX.WE" input="SLICEM_MODES.WE" output="WE_MUX.WE"/>
<!-- ADI1MUX -->
<mux name="ADI1MUX32" input="BSRL.MC31_SRL32 SLICEM_MODES.AI" output="ASRL.DI1_SRL32">
<metadata>
<meta name="fasm_mux">
BSRL.MC31_SRL32 = ALUT.DI1MUX.BDI1_BMC31
SLICEM_MODES.AI = ALUT.DI1MUX.AI
</meta>
</metadata>
<pack_pattern name="SRL32_x2" in_port="BSRL.MC31_SRL32" out_port="ASRL.DI1_SRL32" />
<pack_pattern name="SRL32_x3" in_port="BSRL.MC31_SRL32" out_port="ASRL.DI1_SRL32" />
<pack_pattern name="SRL32_x4" in_port="BSRL.MC31_SRL32" out_port="ASRL.DI1_SRL32" />
</mux>
<!-- BDI1MUX -->
<mux name="BDI1MUX32" input="CSRL.MC31_SRL32 SLICEM_MODES.BI" output="BSRL.DI1_SRL32">
<metadata>
<meta name="fasm_mux">
CSRL.MC31_SRL32 = BLUT.DI1MUX.DI_CMC31
SLICEM_MODES.BI = BLUT.DI1MUX.BI
</meta>
</metadata>
<pack_pattern name="SRL32_x3" in_port="CSRL.MC31_SRL32" out_port="BSRL.DI1_SRL32" />
<pack_pattern name="SRL32_x4" in_port="CSRL.MC31_SRL32" out_port="BSRL.DI1_SRL32" />
</mux>
<!-- CDI1MUX -->
<mux name="CDI1MUX32" input="DSRL.MC31_SRL32 SLICEM_MODES.CI" output="CSRL.DI1_SRL32">
<metadata>
<meta name="fasm_mux">
DSRL.MC31_SRL32 = CLUT.DI1MUX.DI_DMC31
SLICEM_MODES.CI = CLUT.DI1MUX.CI
</meta>
</metadata>
<pack_pattern name="SRL32_x4" in_port="DSRL.MC31_SRL32" out_port="CSRL.DI1_SRL32" />
</mux>
<mux name="ADI1MUX16" input="BSRL.MC31_SRL16 SLICEM_MODES.AI" output="ASRL.DI1_SRL16">
<metadata>
<meta name="fasm_mux">
BSRL.MC31_SRL16 = ALUT.DI1MUX.BDI1_BMC31
SLICEM_MODES.AI = ALUT.DI1MUX.AI
</meta>
</metadata>
</mux>
<!-- BDI1MUX -->
<mux name="BDI1MUX16" input="CSRL.MC31_SRL16 SLICEM_MODES.BI" output="BSRL.DI1_SRL16">
<metadata>
<meta name="fasm_mux">
CSRL.MC31_SRL16 = BLUT.DI1MUX.DI_CMC31
SLICEM_MODES.BI = BLUT.DI1MUX.BI
</meta>
</metadata>
</mux>
<!-- CDI1MUX -->
<mux name="CDI1MUX16" input="DSRL.MC31_SRL16 SLICEM_MODES.CI" output="CSRL.DI1_SRL16">
<metadata>
<meta name="fasm_mux">
DSRL.MC31_SRL16 = CLUT.DI1MUX.DI_DMC31
SLICEM_MODES.CI = CLUT.DI1MUX.CI
</meta>
</metadata>
</mux>
<!-- AMC31 -->
<direct name="ASRL.MC31_to_SLICEM_MODES.AMC31" input="ASRL.MC31" output="SLICEM_MODES.AMC31"/>
<!-- F7AMUX inputs -->
<direct name="F7AMUX_I0" input="BSRL.O6" output="F7AMUX.I0"/>
<direct name="F7AMUX_I1" input="ASRL.O6" output="F7AMUX.I1"/>
<direct name="F7AMUX_S" input="SLICEM_MODES.AX" output="F7AMUX.S" />
<!-- F7BMUX inputs -->
<direct name="F7BMUX_I0" input="DSRL.O6" output="F7BMUX.I0"/>
<direct name="F7BMUX_I1" input="CSRL.O6" output="F7BMUX.I1"/>
<direct name="F7BMUX_S" input="SLICEM_MODES.CX" output="F7BMUX.S" />
<!-- F8MUX inputs -->
<direct name="F8MUX_I0" input="F7BMUX.O" output="F8MUX.I0">
</direct>
<direct name="F8MUX_I1" input="F7AMUX.O" output="F8MUX.I1">
</direct>
<direct name="F8MUX_S" input="SLICEM_MODES.BX" output="F8MUX.S" />
<!-- F7AMUX, F7BMUX and F8MUX outputs -->
<direct name="F7AMUX_O" input="F7AMUX.O" output="SLICEM_MODES.F7AMUX_O" />
<direct name="F7BMUX_O" input="F7BMUX.O" output="SLICEM_MODES.F7BMUX_O" />
<direct name="F8MUX_O" input="F8MUX.O" output="SLICEM_MODES.F8MUX_O" />
</interconnect>
</mode>
<mode name="DRAMs">
<xi:include href="Ndram/d_dram.pb_type.xml"/>
<xi:include href="Ndram/c_dram.pb_type.xml"/>
<xi:include href="Ndram/b_dram.pb_type.xml"/>
<xi:include href="Ndram/a_dram.pb_type.xml"/>
<xi:include href="../common_slice/muxes/f7amux/f7amux.pb_type.xml"/>
<xi:include href="../common_slice/muxes/f7bmux/f7bmux.pb_type.xml"/>
<xi:include href="../common_slice/muxes/f8mux/f8mux.pb_type.xml"/>
<pb_type name="DRAM_8_OUTPUT_STUB" blif_model=".subckt DRAM_8_OUTPUT_STUB" num_pb="1">
<xi:include href="dram_8_output_stub.pb_type.xml"
xpointer="xpointer(pb_type/child::node())" />
<metadata>
<meta name="type">bel</meta>
<meta name="subtype">blackbox</meta>
</metadata>
</pb_type>
<pb_type name="DRAM_4_OUTPUT_STUB" blif_model=".subckt DRAM_4_OUTPUT_STUB" num_pb="2">
<xi:include href="dram_4_output_stub.pb_type.xml"
xpointer="xpointer(pb_type/child::node())" />
<metadata>
<meta name="type">bel</meta>
<meta name="subtype">blackbox</meta>
</metadata>
</pb_type>
<pb_type name="DRAM_2_OUTPUT_STUB" blif_model=".subckt DRAM_2_OUTPUT_STUB" num_pb="6">
<xi:include href="dram_2_output_stub.pb_type.xml"
xpointer="xpointer(pb_type/child::node())" />
<metadata>
<meta name="type">bel</meta>
<meta name="subtype">blackbox</meta>
</metadata>
</pb_type>
<xi:include href="wemux.pb_type.xml"/>
<pb_type name="DI64_STUB" blif_model=".subckt DI64_STUB" num_pb="3">
<xi:include href="di64_stub.pb_type.xml"
xpointer="xpointer(pb_type/child::node())" />
<metadata>
<meta name="type">bel</meta>
<meta name="subtype">blackbox</meta>
</metadata>
</pb_type>
<interconnect>
<!-- The DLUT must be in RAM-mode for any of the RAM's to work.
As a corollary, a DRAM requires the clock, so only turn on the
DRAM if the clock is also connected.
-->
<direct name="AMEMCLK" input="SLICEM_MODES.CLK" output="A_DRAM.CLK">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.CLK = DLUT.RAM
</meta>
</metadata>
</direct>
<direct name="BMEMCLK" input="SLICEM_MODES.CLK" output="B_DRAM.CLK">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.CLK = DLUT.RAM
</meta>
</metadata>
</direct>
<direct name="CMEMCLK" input="SLICEM_MODES.CLK" output="C_DRAM.CLK">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.CLK = DLUT.RAM
</meta>
</metadata>
</direct>
<direct name="DMEMCLK" input="SLICEM_MODES.CLK" output="D_DRAM.CLK" />
<direct name="D1" input="SLICEM_MODES.D1" output="D_DRAM.A[0]" />
<direct name="D2" input="SLICEM_MODES.D2" output="D_DRAM.A[1]" />
<direct name="D3" input="SLICEM_MODES.D3" output="D_DRAM.A[2]" />
<direct name="D4" input="SLICEM_MODES.D4" output="D_DRAM.A[3]" />
<direct name="D5" input="SLICEM_MODES.D5" output="D_DRAM.A[4]" />
<direct name="D6" input="SLICEM_MODES.D6" output="D_DRAM.A[5]" />
<direct name="C1" input="SLICEM_MODES.C1" output="C_DRAM.A[0]" />
<direct name="C2" input="SLICEM_MODES.C2" output="C_DRAM.A[1]" />
<direct name="C3" input="SLICEM_MODES.C3" output="C_DRAM.A[2]" />
<direct name="C4" input="SLICEM_MODES.C4" output="C_DRAM.A[3]" />
<direct name="C5" input="SLICEM_MODES.C5" output="C_DRAM.A[4]" />
<direct name="C6" input="SLICEM_MODES.C6" output="C_DRAM.A[5]" />
<direct name="B1" input="SLICEM_MODES.B1" output="B_DRAM.A[0]" />
<direct name="B2" input="SLICEM_MODES.B2" output="B_DRAM.A[1]" />
<direct name="B3" input="SLICEM_MODES.B3" output="B_DRAM.A[2]" />
<direct name="B4" input="SLICEM_MODES.B4" output="B_DRAM.A[3]" />
<direct name="B5" input="SLICEM_MODES.B5" output="B_DRAM.A[4]" />
<direct name="B6" input="SLICEM_MODES.B6" output="B_DRAM.A[5]" />
<direct name="A1" input="SLICEM_MODES.A1" output="A_DRAM.A[0]" />
<direct name="A2" input="SLICEM_MODES.A2" output="A_DRAM.A[1]" />
<direct name="A3" input="SLICEM_MODES.A3" output="A_DRAM.A[2]" />
<direct name="A4" input="SLICEM_MODES.A4" output="A_DRAM.A[3]" />
<direct name="A5" input="SLICEM_MODES.A5" output="A_DRAM.A[4]" />
<direct name="A6" input="SLICEM_MODES.A6" output="A_DRAM.A[5]" />
<!-- W Address lines come in on the DLUT pins and go to all the LUTs.
-->
<direct name="WC1" input="SLICEM_MODES.D1" output="C_DRAM.WA[0]" />
<direct name="WC2" input="SLICEM_MODES.D2" output="C_DRAM.WA[1]" />
<direct name="WC3" input="SLICEM_MODES.D3" output="C_DRAM.WA[2]" />
<direct name="WC4" input="SLICEM_MODES.D4" output="C_DRAM.WA[3]" />
<direct name="WC5" input="SLICEM_MODES.D5" output="C_DRAM.WA[4]" />
<direct name="WC6" input="SLICEM_MODES.D6" output="C_DRAM.WA[5]" />
<direct name="WB1" input="SLICEM_MODES.D1" output="B_DRAM.WA[0]" />
<direct name="WB2" input="SLICEM_MODES.D2" output="B_DRAM.WA[1]" />
<direct name="WB3" input="SLICEM_MODES.D3" output="B_DRAM.WA[2]" />
<direct name="WB4" input="SLICEM_MODES.D4" output="B_DRAM.WA[3]" />
<direct name="WB5" input="SLICEM_MODES.D5" output="B_DRAM.WA[4]" />
<direct name="WB6" input="SLICEM_MODES.D6" output="B_DRAM.WA[5]" />
<direct name="WA1" input="SLICEM_MODES.D1" output="A_DRAM.WA[0]" />
<direct name="WA2" input="SLICEM_MODES.D2" output="A_DRAM.WA[1]" />
<direct name="WA3" input="SLICEM_MODES.D3" output="A_DRAM.WA[2]" />
<direct name="WA4" input="SLICEM_MODES.D4" output="A_DRAM.WA[3]" />
<direct name="WA5" input="SLICEM_MODES.D5" output="A_DRAM.WA[4]" />
<direct name="WA6" input="SLICEM_MODES.D6" output="A_DRAM.WA[5]" />
<!-- WA7 and WA8 should only be used in this mode if using 256x1S,
which consumes the entire slice. -->
<direct name="D_WA7" input="SLICEM_MODES.WA7" output="D_DRAM.WA7" />
<direct name="C_WA7" input="SLICEM_MODES.WA7" output="C_DRAM.WA[6]" />
<direct name="B_WA7" input="SLICEM_MODES.WA7" output="B_DRAM.WA[6]" />
<direct name="A_WA7" input="SLICEM_MODES.WA7" output="A_DRAM.WA[6]" />
<direct name="D_WA8" input="SLICEM_MODES.WA8" output="D_DRAM.WA8" />
<direct name="C_WA8" input="SLICEM_MODES.WA8" output="C_DRAM.WA[7]" />
<direct name="B_WA8" input="SLICEM_MODES.WA8" output="B_DRAM.WA[7]" />
<direct name="A_WA8" input="SLICEM_MODES.WA8" output="A_DRAM.WA[7]" />
<!-- The DI64_STUB's enforce the required that in the DPO RAM64 case,
the SPO RAM64 **must** use the same site pin as the DPO RAM64.
-->
<direct name="CI_STUB" input="SLICEM_MODES.DI" output="DI64_STUB[0].DI" />
<direct name="BI_STUB" input="SLICEM_MODES.DI" output="DI64_STUB[1].DI" />
<direct name="AI_STUB" input="B_DRAM.DO1" output="DI64_STUB[2].DI" />
<!-- DI1 inputs -->
<direct name="D_DI1" input="SLICEM_MODES.DI" output="D_DRAM.DI1" />
<mux name="CDI1MUX" input="SLICEM_MODES.DI DI64_STUB[0].DO SLICEM_MODES.CI" output="C_DRAM.DI1">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.DI = CLUT.DI1MUX.DI_DMC31
DI64_STUB[0].DO = CLUT.DI1MUX.DI_DMC31
SLICEM_MODES.CI = CLUT.DI1MUX.CI
</meta>
</metadata>
<pack_pattern in_port="DI64_STUB[0].DO" name="DRAM_DP" out_port="C_DRAM.DI1" />
</mux>
<mux name="BDI1MUX" input="SLICEM_MODES.DI DI64_STUB[1].DO SLICEM_MODES.BI" output="B_DRAM.DI1">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.DI = BLUT.DI1MUX.DI_CMC31
DI64_STUB[1].DO = BLUT.DI1MUX.DI_CMC31
SLICEM_MODES.BI = BLUT.DI1MUX.BI
</meta>
</metadata>
</mux>
<mux name="ADI1MUX" input="SLICEM_MODES.DI DI64_STUB[2].DO SLICEM_MODES.BI SLICEM_MODES.AI" output="A_DRAM.DI1">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.DI = ALUT.DI1MUX.BDI1_BMC31,BLUT.DI1MUX.DI_CMC31
DI64_STUB[2].DO = ALUT.DI1MUX.BDI1_BMC31
SLICEM_MODES.BI = ALUT.DI1MUX.BDI1_BMC31,BLUT.DI1MUX.BI
SLICEM_MODES.AI = ALUT.DI1MUX.AI
</meta>
</metadata>
<pack_pattern in_port="DI64_STUB[2].DO" name="DRAM_DP" out_port="A_DRAM.DI1" />
</mux>
<!-- DI2 inputs -->
<direct name="D_DI2" input="SLICEM_MODES.DX" output="D_DRAM.DI2" />
<direct name="C_DI2" input="SLICEM_MODES.CX" output="C_DRAM.DI2" />
<direct name="B_DI2" input="SLICEM_MODES.BX" output="B_DRAM.DI2" />
<direct name="A_DI2" input="SLICEM_MODES.AX" output="A_DRAM.DI2" />
<!-- WE inputs -->
<direct name="CE_TO_WE_MUX" input="SLICEM_MODES.CE" output="WE_MUX.CE"/>
<direct name="WE_TO_WE_MUX" input="SLICEM_MODES.WE" output="WE_MUX.WE"/>
<direct name="WE1" input="WE_MUX.WE_OUT" output="A_DRAM.WE"/>
<direct name="WE2" input="WE_MUX.WE_OUT" output="B_DRAM.WE"/>
<direct name="WE3" input="WE_MUX.WE_OUT" output="C_DRAM.WE"/>
<direct name="WE4" input="WE_MUX.WE_OUT" output="D_DRAM.WE"/>
<!-- Outputs -->
<!-- 32 bits, upper half, interleaved -->
<direct name="SPO_0" input="D_DRAM.SO6_32" output="DRAM_2_OUTPUT_STUB[0].SPO">
<pack_pattern in_port="D_DRAM.SO6_32" name="DRAM_DP_32_HI" out_port="DRAM_2_OUTPUT_STUB[0].SPO" />
</direct>
<direct name="DPO_0" input="C_DRAM.DO6_32" output="DRAM_2_OUTPUT_STUB[0].DPO">
<pack_pattern in_port="C_DRAM.DO6_32" name="DRAM_DP_32_HI" out_port="DRAM_2_OUTPUT_STUB[0].DPO" />
</direct>
<direct name="SPO_1" input="D_DRAM.SO5_32" output="DRAM_2_OUTPUT_STUB[1].SPO">
<pack_pattern in_port="D_DRAM.SO5_32" name="DRAM_DP_32_HI" out_port="DRAM_2_OUTPUT_STUB[1].SPO" />
</direct>
<direct name="DPO_1" input="C_DRAM.DO5_32" output="DRAM_2_OUTPUT_STUB[1].DPO">
<pack_pattern in_port="C_DRAM.DO5_32" name="DRAM_DP_32_HI" out_port="DRAM_2_OUTPUT_STUB[1].DPO" />
</direct>
<!-- 32 bits, lower half, interleaved -->
<direct name="SPO_2" input="B_DRAM.DO6_32" output="DRAM_2_OUTPUT_STUB[2].SPO">
<pack_pattern in_port="B_DRAM.DO6_32" name="DRAM_DP_32_LO" out_port="DRAM_2_OUTPUT_STUB[2].SPO" />
</direct>
<direct name="DPO_2" input="A_DRAM.DO6_32" output="DRAM_2_OUTPUT_STUB[2].DPO">
<pack_pattern in_port="A_DRAM.DO6_32" name="DRAM_DP_32_LO" out_port="DRAM_2_OUTPUT_STUB[2].DPO" />
</direct>
<direct name="SPO_3" input="B_DRAM.DO5_32" output="DRAM_2_OUTPUT_STUB[3].SPO">
<pack_pattern in_port="B_DRAM.DO5_32" name="DRAM_DP_32_LO" out_port="DRAM_2_OUTPUT_STUB[3].SPO" />
</direct>
<direct name="DPO_3" input="A_DRAM.DO5_32" output="DRAM_2_OUTPUT_STUB[3].DPO">
<pack_pattern in_port="A_DRAM.DO5_32" name="DRAM_DP_32_LO" out_port="DRAM_2_OUTPUT_STUB[3].DPO" />
</direct>
<!-- 64 bits -->
<direct name="SPO_4" input="D_DRAM.SO6" output="DRAM_2_OUTPUT_STUB[4].SPO">
<pack_pattern in_port="D_DRAM.SO6" name="DRAM_DP" out_port="DRAM_2_OUTPUT_STUB[4].SPO" />
</direct>
<direct name="DPO_4" input="C_DRAM.DO6" output="DRAM_2_OUTPUT_STUB[4].DPO">
<pack_pattern in_port="C_DRAM.DO6" name="DRAM_DP" out_port="DRAM_2_OUTPUT_STUB[4].DPO" />
</direct>
<direct name="SPO_5" input="B_DRAM.DO6" output="DRAM_2_OUTPUT_STUB[5].SPO">
<pack_pattern in_port="B_DRAM.DO6" name="DRAM_DP" out_port="DRAM_2_OUTPUT_STUB[5].SPO" />
</direct>
<direct name="DPO_5" input="A_DRAM.DO6" output="DRAM_2_OUTPUT_STUB[5].DPO">
<pack_pattern in_port="A_DRAM.DO6" name="DRAM_DP" out_port="DRAM_2_OUTPUT_STUB[5].DPO" />
</direct>
<direct name="DOD32" input="D_DRAM.SO6_32" output="DRAM_4_OUTPUT_STUB[0].DOD">
<pack_pattern in_port="D_DRAM.SO6_32" name="DRAM_QP_32" out_port="DRAM_4_OUTPUT_STUB[0].DOD" />
</direct>
<direct name="DOC32" input="C_DRAM.DO6_32" output="DRAM_4_OUTPUT_STUB[0].DOC">
<pack_pattern in_port="C_DRAM.DO6_32" name="DRAM_QP_32" out_port="DRAM_4_OUTPUT_STUB[0].DOC" />
</direct>
<direct name="DOB32" input="B_DRAM.DO6_32" output="DRAM_4_OUTPUT_STUB[0].DOB">
<pack_pattern in_port="B_DRAM.DO6_32" name="DRAM_QP_32" out_port="DRAM_4_OUTPUT_STUB[0].DOB" />
</direct>
<direct name="DOA32" input="A_DRAM.DO6_32" output="DRAM_4_OUTPUT_STUB[0].DOA">
<pack_pattern in_port="A_DRAM.DO6_32" name="DRAM_QP_32" out_port="DRAM_4_OUTPUT_STUB[0].DOA" />
</direct>
<direct name="DOD" input="D_DRAM.SO6" output="DRAM_4_OUTPUT_STUB[1].DOD">
<pack_pattern in_port="D_DRAM.SO6" name="DRAM_QP" out_port="DRAM_4_OUTPUT_STUB[1].DOD" />
</direct>
<direct name="DOC" input="C_DRAM.DO6" output="DRAM_4_OUTPUT_STUB[1].DOC">
<pack_pattern in_port="C_DRAM.DO6" name="DRAM_QP" out_port="DRAM_4_OUTPUT_STUB[1].DOC" />
</direct>
<direct name="DOB" input="B_DRAM.DO6" output="DRAM_4_OUTPUT_STUB[1].DOB">
<pack_pattern in_port="B_DRAM.DO6" name="DRAM_QP" out_port="DRAM_4_OUTPUT_STUB[1].DOB" />
</direct>
<direct name="DOA" input="A_DRAM.DO6" output="DRAM_4_OUTPUT_STUB[1].DOA">
<pack_pattern in_port="A_DRAM.DO6" name="DRAM_QP" out_port="DRAM_4_OUTPUT_STUB[1].DOA" />
</direct>
<direct name="DOD32_HI" input="D_DRAM.SO6_32" output="DRAM_8_OUTPUT_STUB.DOD1">
<pack_pattern in_port="D_DRAM.SO6_32" name="DRAM_8O_32" out_port="DRAM_8_OUTPUT_STUB.DOD1" />
</direct>
<direct name="DOC32_HI" input="C_DRAM.DO6_32" output="DRAM_8_OUTPUT_STUB.DOC1">
<pack_pattern in_port="C_DRAM.DO6_32" name="DRAM_8O_32" out_port="DRAM_8_OUTPUT_STUB.DOC1" />
</direct>
<direct name="DOB32_HI" input="B_DRAM.DO6_32" output="DRAM_8_OUTPUT_STUB.DOB1">
<pack_pattern in_port="B_DRAM.DO6_32" name="DRAM_8O_32" out_port="DRAM_8_OUTPUT_STUB.DOB1" />
</direct>
<direct name="DOA32_HI" input="A_DRAM.DO6_32" output="DRAM_8_OUTPUT_STUB.DOA1">
<pack_pattern in_port="A_DRAM.DO6_32" name="DRAM_8O_32" out_port="DRAM_8_OUTPUT_STUB.DOA1" />
</direct>
<direct name="DOD32_LO" input="D_DRAM.SO5_32" output="DRAM_8_OUTPUT_STUB.DOD0">
<pack_pattern in_port="D_DRAM.SO5_32" name="DRAM_8O_32" out_port="DRAM_8_OUTPUT_STUB.DOD0" />
</direct>
<direct name="DOC32_LO" input="C_DRAM.DO5_32" output="DRAM_8_OUTPUT_STUB.DOC0">
<pack_pattern in_port="C_DRAM.DO5_32" name="DRAM_8O_32" out_port="DRAM_8_OUTPUT_STUB.DOC0" />
</direct>
<direct name="DOB32_LO" input="B_DRAM.DO5_32" output="DRAM_8_OUTPUT_STUB.DOB0">
<pack_pattern in_port="B_DRAM.DO5_32" name="DRAM_8O_32" out_port="DRAM_8_OUTPUT_STUB.DOB0" />
</direct>
<direct name="DOA32_LO" input="A_DRAM.DO5_32" output="DRAM_8_OUTPUT_STUB.DOA0">
<pack_pattern in_port="A_DRAM.DO5_32" name="DRAM_8O_32" out_port="DRAM_8_OUTPUT_STUB.DOA0" />
</direct>
<mux name="DO6" input="D_DRAM.O6 DRAM_2_OUTPUT_STUB[0].SPO_OUT DRAM_2_OUTPUT_STUB[4].SPO_OUT DRAM_4_OUTPUT_STUB[0].DOD_OUT DRAM_4_OUTPUT_STUB[1].DOD_OUT DRAM_8_OUTPUT_STUB.DOD1_OUT"
output="SLICEM_MODES.DO6" />
<mux name="DO5" input="D_DRAM.O5 DRAM_2_OUTPUT_STUB[1].SPO_OUT DRAM_8_OUTPUT_STUB.DOD0_OUT"
output="SLICEM_MODES.DO5" />
<mux name="CO6" input="C_DRAM.O6 DRAM_2_OUTPUT_STUB[0].DPO_OUT DRAM_2_OUTPUT_STUB[4].DPO_OUT DRAM_4_OUTPUT_STUB[0].DOC_OUT DRAM_4_OUTPUT_STUB[1].DOC_OUT DRAM_8_OUTPUT_STUB.DOC1_OUT"
output="SLICEM_MODES.CO6" />
<mux name="CO5" input="C_DRAM.O5 DRAM_2_OUTPUT_STUB[1].DPO_OUT DRAM_8_OUTPUT_STUB.DOC0_OUT"
output="SLICEM_MODES.CO5" />
<mux name="BO6" input="B_DRAM.O6 DRAM_2_OUTPUT_STUB[2].SPO_OUT DRAM_2_OUTPUT_STUB[5].SPO_OUT DRAM_4_OUTPUT_STUB[0].DOB_OUT DRAM_4_OUTPUT_STUB[1].DOB_OUT DRAM_8_OUTPUT_STUB.DOB1_OUT"
output="SLICEM_MODES.BO6" />
<mux name="BO5" input="B_DRAM.O5 DRAM_2_OUTPUT_STUB[3].SPO_OUT DRAM_8_OUTPUT_STUB.DOB0_OUT"
output="SLICEM_MODES.BO5" />
<mux name="AO6" input="A_DRAM.O6 DRAM_2_OUTPUT_STUB[2].DPO_OUT DRAM_2_OUTPUT_STUB[5].DPO_OUT DRAM_4_OUTPUT_STUB[0].DOA_OUT DRAM_4_OUTPUT_STUB[1].DOA_OUT DRAM_8_OUTPUT_STUB.DOA1_OUT"
output="SLICEM_MODES.AO6" />
<mux name="AO5" input="A_DRAM.O5 DRAM_2_OUTPUT_STUB[3].DPO_OUT DRAM_8_OUTPUT_STUB.DOA0_OUT"
output="SLICEM_MODES.AO5" />
<!-- F7AMUX inputs -->
<direct name="F7AMUX_I0" input="B_DRAM.DO6" output="F7AMUX.I0">
<pack_pattern in_port="B_DRAM.DO6" name="DRAM256" out_port="F7AMUX.I0"/>
</direct>
<direct name="F7AMUX_I1" input="A_DRAM.DO6" output="F7AMUX.I1">
<pack_pattern in_port="A_DRAM.DO6" name="DRAM256" out_port="F7AMUX.I1"/>
</direct>
<direct name="F7AMUX_S" input="SLICEM_MODES.AX" output="F7AMUX.S" />
<!-- F7BMUX inputs -->
<direct name="F7BMUX_I0" input="D_DRAM.SO6" output="F7BMUX.I0">
<pack_pattern in_port="D_DRAM.SO6" name="DRAM256" out_port="F7BMUX.I0"/>
</direct>
<direct name="F7BMUX_I1" input="C_DRAM.DO6" output="F7BMUX.I1">
<pack_pattern in_port="C_DRAM.DO6" name="DRAM256" out_port="F7BMUX.I1"/>
</direct>
<direct name="F7BMUX_S" input="SLICEM_MODES.CX" output="F7BMUX.S" />
<!-- F8MUX inputs -->
<direct name="F8MUX_I0" input="F7BMUX.O" output="F8MUX.I0">
<pack_pattern in_port="F7BMUX.O" name="DRAM256" out_port="F8MUX.I0"/>
</direct>
<direct name="F8MUX_I1" input="F7AMUX.O" output="F8MUX.I1">
<pack_pattern in_port="F7AMUX.O" name="DRAM256" out_port="F8MUX.I1"/>
</direct>
<direct name="F8MUX_S" input="SLICEM_MODES.BX" output="F8MUX.S" />
<direct name="F7AMUX_O" input="F7AMUX.O" output="SLICEM_MODES.F7AMUX_O" />
<direct name="F7BMUX_O" input="F7BMUX.O" output="SLICEM_MODES.F7BMUX_O" />
<direct name="F8MUX_O" input="F8MUX.O" output="SLICEM_MODES.F8MUX_O" />
</interconnect>
</mode>
<mode name="DRAM128">
<xi:include href="Ndram/d_dram128.pb_type.xml"/>
<xi:include href="Ndram/c_dram128.pb_type.xml"/>
<xi:include href="Ndram/b_dram128.pb_type.xml"/>
<xi:include href="Ndram/a_dram128.pb_type.xml"/>
<xi:include href="../common_slice/muxes/f7amux/f7amux.pb_type.xml"/>
<xi:include href="../common_slice/muxes/f7bmux/f7bmux.pb_type.xml"/>
<xi:include href="dram_2_output_stub.pb_type.xml"/>
<pb_type name="WE_MUX" num_pb="1">
<input name="CE" num_pins="1"/>
<input name="WE" num_pins="1"/>
<output name="WE_OUT" num_pins="1"/>
<interconnect>
<mux name="WE_MUX" input="WE_MUX.CE WE_MUX.WE" output="WE_MUX.WE_OUT">
<metadata>
<meta name="fasm_mux">
WE_MUX.CE = WEMUX.CE
WE_MUX.WE = NULL
</meta>
</metadata>
</mux>
</interconnect>
<metadata>
<meta name="type">bel</meta>
<meta name="subtype">routing</meta>
</metadata>
</pb_type>
<interconnect>
<direct name="AMEMCLK" input="SLICEM_MODES.CLK" output="A_DRAM128.CLK"/>
<direct name="BMEMCLK" input="SLICEM_MODES.CLK" output="B_DRAM128.CLK"/>
<direct name="CMEMCLK" input="SLICEM_MODES.CLK" output="C_DRAM128.CLK"/>
<direct name="DMEMCLK" input="SLICEM_MODES.CLK" output="D_DRAM128.CLK"/>
<direct name="D1" input="SLICEM_MODES.D1" output="D_DRAM128.A[0]" />
<direct name="D2" input="SLICEM_MODES.D2" output="D_DRAM128.A[1]" />
<direct name="D3" input="SLICEM_MODES.D3" output="D_DRAM128.A[2]" />
<direct name="D4" input="SLICEM_MODES.D4" output="D_DRAM128.A[3]" />
<direct name="D5" input="SLICEM_MODES.D5" output="D_DRAM128.A[4]" />
<direct name="D6" input="SLICEM_MODES.D6" output="D_DRAM128.A[5]" />
<direct name="C1" input="SLICEM_MODES.C1" output="C_DRAM128.A[0]" />
<direct name="C2" input="SLICEM_MODES.C2" output="C_DRAM128.A[1]" />
<direct name="C3" input="SLICEM_MODES.C3" output="C_DRAM128.A[2]" />
<direct name="C4" input="SLICEM_MODES.C4" output="C_DRAM128.A[3]" />
<direct name="C5" input="SLICEM_MODES.C5" output="C_DRAM128.A[4]" />
<direct name="C6" input="SLICEM_MODES.C6" output="C_DRAM128.A[5]" />
<direct name="B1" input="SLICEM_MODES.B1" output="B_DRAM128.A[0]" />
<direct name="B2" input="SLICEM_MODES.B2" output="B_DRAM128.A[1]" />
<direct name="B3" input="SLICEM_MODES.B3" output="B_DRAM128.A[2]" />
<direct name="B4" input="SLICEM_MODES.B4" output="B_DRAM128.A[3]" />
<direct name="B5" input="SLICEM_MODES.B5" output="B_DRAM128.A[4]" />
<direct name="B6" input="SLICEM_MODES.B6" output="B_DRAM128.A[5]" />
<direct name="A1" input="SLICEM_MODES.A1" output="A_DRAM128.A[0]" />
<direct name="A2" input="SLICEM_MODES.A2" output="A_DRAM128.A[1]" />
<direct name="A3" input="SLICEM_MODES.A3" output="A_DRAM128.A[2]" />
<direct name="A4" input="SLICEM_MODES.A4" output="A_DRAM128.A[3]" />
<direct name="A5" input="SLICEM_MODES.A5" output="A_DRAM128.A[4]" />
<direct name="A6" input="SLICEM_MODES.A6" output="A_DRAM128.A[5]" />
<!-- W Address lines come in on the DLUT pins and go to all the LUTs.
-->
<direct name="WD7" input="SLICEM_MODES.WA7" output="D_DRAM128.WA7" />
<direct name="WC1" input="SLICEM_MODES.D1" output="C_DRAM128.WA[0]" />
<direct name="WC2" input="SLICEM_MODES.D2" output="C_DRAM128.WA[1]" />
<direct name="WC3" input="SLICEM_MODES.D3" output="C_DRAM128.WA[2]" />
<direct name="WC4" input="SLICEM_MODES.D4" output="C_DRAM128.WA[3]" />
<direct name="WC5" input="SLICEM_MODES.D5" output="C_DRAM128.WA[4]" />
<direct name="WC6" input="SLICEM_MODES.D6" output="C_DRAM128.WA[5]" />
<direct name="WC7" input="SLICEM_MODES.WA7" output="C_DRAM128.WA[6]" />
<direct name="WB1" input="SLICEM_MODES.D1" output="B_DRAM128.WA[0]" />
<direct name="WB2" input="SLICEM_MODES.D2" output="B_DRAM128.WA[1]" />
<direct name="WB3" input="SLICEM_MODES.D3" output="B_DRAM128.WA[2]" />
<direct name="WB4" input="SLICEM_MODES.D4" output="B_DRAM128.WA[3]" />
<direct name="WB5" input="SLICEM_MODES.D5" output="B_DRAM128.WA[4]" />
<direct name="WB6" input="SLICEM_MODES.D6" output="B_DRAM128.WA[5]" />
<direct name="WB7" input="SLICEM_MODES.WA7" output="B_DRAM128.WA[6]" />
<direct name="WA1" input="SLICEM_MODES.D1" output="A_DRAM128.WA[0]" />
<direct name="WA2" input="SLICEM_MODES.D2" output="A_DRAM128.WA[1]" />
<direct name="WA3" input="SLICEM_MODES.D3" output="A_DRAM128.WA[2]" />
<direct name="WA4" input="SLICEM_MODES.D4" output="A_DRAM128.WA[3]" />
<direct name="WA5" input="SLICEM_MODES.D5" output="A_DRAM128.WA[4]" />
<direct name="WA6" input="SLICEM_MODES.D6" output="A_DRAM128.WA[5]" />
<direct name="WA7" input="SLICEM_MODES.WA7" output="A_DRAM128.WA[6]" />
<!-- Direct DI1 inputs -->
<direct name="DI" input="SLICEM_MODES.DI" output="D_DRAM128.DI1" />
<mux name="CDI1MUX" input="SLICEM_MODES.DI SLICEM_MODES.CI" output="C_DRAM128.DI1">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.DI = CLUT.DI1MUX.DI_DMC31
SLICEM_MODES.CI = CLUT.DI1MUX.CI
</meta>
</metadata>
</mux>
<mux name="BDI1MUX" input="SLICEM_MODES.DI SLICEM_MODES.BI" output="B_DRAM128.DI1">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.DI = BLUT.DI1MUX.DI_CMC31
SLICEM_MODES.BI = BLUT.DI1MUX.BI
</meta>
</metadata>
</mux>
<!-- TODO: ensure BLUT.DI1MUX is set correctly for SLICEM_MODES.DI/BI
For now, the FASM features are emitted to ensure that the mux
is set correctly, and it there is a mux conflict it will arise
during fasm2frames.
-->
<mux name="ADI1MUX" input="SLICEM_MODES.DI SLICEM_MODES.BI SLICEM_MODES.AI" output="A_DRAM128.DI1">
<metadata>
<meta name="fasm_mux">
SLICEM_MODES.DI = ALUT.DI1MUX.BDI1_BMC31,BLUT.DI1MUX.DI_CMC31
SLICEM_MODES.BI = ALUT.DI1MUX.BDI1_BMC31,BLUT.DI1MUX.BI
SLICEM_MODES.AI = ALUT.DI1MUX.AI
</meta>
</metadata>
</mux>
<!-- WE inputs -->
<direct name="CE_TO_WE_MUX" input="SLICEM_MODES.CE" output="WE_MUX.CE"/>
<direct name="WE_TO_WE_MUX" input="SLICEM_MODES.WE" output="WE_MUX.WE"/>
<direct name="WE1" input="WE_MUX.WE_OUT" output="A_DRAM128.WE"/>
<direct name="WE2" input="WE_MUX.WE_OUT" output="B_DRAM128.WE"/>
<direct name="WE3" input="WE_MUX.WE_OUT" output="C_DRAM128.WE"/>
<direct name="WE4" input="WE_MUX.WE_OUT" output="D_DRAM128.WE"/>
<!-- Outputs -->
<direct name="DO6" input="D_DRAM128.O6" output="SLICEM_MODES.DO6" />
<direct name="CO6" input="C_DRAM128.O6" output="SLICEM_MODES.CO6" />
<direct name="BO6" input="B_DRAM128.O6" output="SLICEM_MODES.BO6" />
<direct name="AO6" input="A_DRAM128.O6" output="SLICEM_MODES.AO6" />
<!-- F7AMUX inputs -->
<mux name="F7AMUX_I0" input="B_DRAM128.DO6" output="F7AMUX.I0">
<pack_pattern in_port="B_DRAM128.DO6" name="DRAM128" out_port="F7AMUX.I0"/>
<pack_pattern in_port="B_DRAM128.DO6" name="DRAM128_DP" out_port="F7AMUX.I0"/>
</mux>
<direct name="F7AMUX_I1" input="A_DRAM128.DO6" output="F7AMUX.I1">
<pack_pattern in_port="A_DRAM128.DO6" name="DRAM128" out_port="F7AMUX.I1"/>
<pack_pattern in_port="A_DRAM128.DO6" name="DRAM128_DP" out_port="F7AMUX.I1"/>
</direct>
<direct name="F7AMUX_S" input="SLICEM_MODES.AX" output="F7AMUX.S" />
<!-- F7BMUX inputs -->
<direct name="F7BMUX_I0" input="D_DRAM128.O6" output="F7BMUX.I0">
<pack_pattern in_port="D_DRAM128.O6" name="DRAM128" out_port="F7BMUX.I0"/>
<pack_pattern in_port="D_DRAM128.O6" name="DRAM128_DP" out_port="F7BMUX.I0"/>
</direct>
<direct name="F7BMUX_I1" input="C_DRAM128.DO6" output="F7BMUX.I1">
<pack_pattern in_port="C_DRAM128.DO6" name="DRAM128" out_port="F7BMUX.I1"/>
<pack_pattern in_port="C_DRAM128.DO6" name="DRAM128_DP" out_port="F7BMUX.I1"/>
</direct>
<direct name="F7BMUX_S" input="SLICEM_MODES.CX" output="F7BMUX.S" />
<direct name="DPO" input="F7AMUX.O" output="DRAM_2_OUTPUT_STUB.DPO">
<pack_pattern in_port="F7AMUX.O" name="DRAM128_DP" out_port="DRAM_2_OUTPUT_STUB.DPO" />
</direct>
<direct name="SPO" input="F7BMUX.O" output="DRAM_2_OUTPUT_STUB.SPO">
<pack_pattern in_port="F7BMUX.O" name="DRAM128_DP" out_port="DRAM_2_OUTPUT_STUB.SPO" />
</direct>
<mux name="F7AMUX_O" input="F7AMUX.O DRAM_2_OUTPUT_STUB.DPO_OUT" output="SLICEM_MODES.F7AMUX_O" />
<mux name="F7BMUX_O" input="F7BMUX.O DRAM_2_OUTPUT_STUB.SPO_OUT" output="SLICEM_MODES.F7BMUX_O" />
</interconnect>
</mode>
<metadata>
<meta name="type">block</meta>
<meta name="subtype">ignore</meta>
</metadata>
</pb_type>
<interconnect>
<!-- SLICEM_MODES inputs -->
<direct name="DI" input="SLICEM.DI" output="SLICEM_MODES.DI" />
<direct name="DX2" input="SLICEM.DX" output="SLICEM_MODES.DX" />
<direct name="D1" input="SLICEM.D1" output="SLICEM_MODES.D1" />
<direct name="D2" input="SLICEM.D2" output="SLICEM_MODES.D2" />
<direct name="D3" input="SLICEM.D3" output="SLICEM_MODES.D3" />
<direct name="D4" input="SLICEM.D4" output="SLICEM_MODES.D4" />
<direct name="D5" input="SLICEM.D5" output="SLICEM_MODES.D5" />
<direct name="D6" input="SLICEM.D6" output="SLICEM_MODES.D6" />
<direct name="CI" input="SLICEM.CI" output="SLICEM_MODES.CI" />
<direct name="CX2" input="SLICEM.CX" output="SLICEM_MODES.CX" />
<direct name="C1" input="SLICEM.C1" output="SLICEM_MODES.C1" />
<direct name="C2" input="SLICEM.C2" output="SLICEM_MODES.C2" />
<direct name="C3" input="SLICEM.C3" output="SLICEM_MODES.C3" />
<direct name="C4" input="SLICEM.C4" output="SLICEM_MODES.C4" />
<direct name="C5" input="SLICEM.C5" output="SLICEM_MODES.C5" />
<direct name="C6" input="SLICEM.C6" output="SLICEM_MODES.C6" />
<direct name="BI" input="SLICEM.BI" output="SLICEM_MODES.BI" />
<direct name="BX2" input="SLICEM.BX" output="SLICEM_MODES.BX" />
<direct name="B1" input="SLICEM.B1" output="SLICEM_MODES.B1" />
<direct name="B2" input="SLICEM.B2" output="SLICEM_MODES.B2" />
<direct name="B3" input="SLICEM.B3" output="SLICEM_MODES.B3" />
<direct name="B4" input="SLICEM.B4" output="SLICEM_MODES.B4" />
<direct name="B5" input="SLICEM.B5" output="SLICEM_MODES.B5" />
<direct name="B6" input="SLICEM.B6" output="SLICEM_MODES.B6" />
<direct name="AI" input="SLICEM.AI" output="SLICEM_MODES.AI" />
<direct name="AX2" input="SLICEM.AX" output="SLICEM_MODES.AX" />
<direct name="A1" input="SLICEM.A1" output="SLICEM_MODES.A1" />
<direct name="A2" input="SLICEM.A2" output="SLICEM_MODES.A2" />
<direct name="A3" input="SLICEM.A3" output="SLICEM_MODES.A3" />
<direct name="A4" input="SLICEM.A4" output="SLICEM_MODES.A4" />
<direct name="A5" input="SLICEM.A5" output="SLICEM_MODES.A5" />
<direct name="A6" input="SLICEM.A6" output="SLICEM_MODES.A6" />
<direct name="CK2" input="SLICEM.CLK" output="SLICEM_MODES.CLK"/>
<direct name="CE2" input="SLICEM.CE" output="SLICEM_MODES.CE"/>
<direct name="WE2" input="SLICEM.WE" output="SLICEM_MODES.WE"/>
<!-- SLICEM_MODES Outputs -->
<direct name="DO6" input="SLICEM_MODES.DO6" output="COMMON_SLICE.DO6" />
<direct name="DO5" input="SLICEM_MODES.DO5" output="COMMON_SLICE.DO5" />
<direct name="CO6" input="SLICEM_MODES.CO6" output="COMMON_SLICE.CO6" />
<direct name="CO5" input="SLICEM_MODES.CO5" output="COMMON_SLICE.CO5" />
<direct name="BO6" input="SLICEM_MODES.BO6" output="COMMON_SLICE.BO6" />
<direct name="BO5" input="SLICEM_MODES.BO5" output="COMMON_SLICE.BO5" />
<direct name="AO6" input="SLICEM_MODES.AO6" output="COMMON_SLICE.AO6" />
<direct name="AO5" input="SLICEM_MODES.AO5" output="COMMON_SLICE.AO5" />
<direct name="F7AMUX_O" input="SLICEM_MODES.F7AMUX_O" output="COMMON_SLICE.F7AMUX_O" />
<direct name="F7BMUX_O" input="SLICEM_MODES.F7BMUX_O" output="COMMON_SLICE.F7BMUX_O" />
<direct name="F8MUX_O" input="SLICEM_MODES.F8MUX_O" output="COMMON_SLICE.F8MUX_O" />
<direct name="SLICEM_MODES.AMC31_to_SLICEM.AMC31" input="SLICEM_MODES.AMC31" output="COMMON_SLICE.AMC31"/>
<!-- A-DX inputs -->
<direct name="DX" input="SLICEM.DX" output="COMMON_SLICE.DX" />
<direct name="CX" input="SLICEM.CX" output="COMMON_SLICE.CX" />
<direct name="BX" input="SLICEM.BX" output="COMMON_SLICE.BX" />
<direct name="AX" input="SLICEM.AX" output="COMMON_SLICE.AX" />
<!-- [A-F]Q outputs -->
<direct name="AQ" input="COMMON_SLICE.AQ" output="SLICEM.AQ" />
<direct name="BQ" input="COMMON_SLICE.BQ" output="SLICEM.BQ" />
<direct name="CQ" input="COMMON_SLICE.CQ" output="SLICEM.CQ" />
<direct name="DQ" input="COMMON_SLICE.DQ" output="SLICEM.DQ" />
<!-- A-D output -->
<direct name="SLICEM_DOUT" input="COMMON_SLICE.D" output="SLICEM.D" />
<direct name="SLICEM_COUT" input="COMMON_SLICE.C" output="SLICEM.C" />
<direct name="SLICEM_BOUT" input="COMMON_SLICE.B" output="SLICEM.B" />
<direct name="SLICEM_AOUT" input="COMMON_SLICE.A" output="SLICEM.A" />
<!-- AMUX-DMUX output -->
<direct name="SLICEM_DMUX" input="COMMON_SLICE.DMUX" output="SLICEM.DMUX" />
<direct name="SLICEM_CMUX" input="COMMON_SLICE.CMUX" output="SLICEM.CMUX" />
<direct name="SLICEM_BMUX" input="COMMON_SLICE.BMUX" output="SLICEM.BMUX" />
<direct name="SLICEM_AMUX" input="COMMON_SLICE.AMUX" output="SLICEM.AMUX" />
<!-- Carry -->
<direct name="CIN" input="SLICEM.CIN" output="COMMON_SLICE.CIN" />
<direct name="COUT" input="COMMON_SLICE.COUT" output="SLICEM.COUT" />
<!-- Clock, Clock Enable and Reset -->
<direct name="CK" input="SLICEM.CLK" output="COMMON_SLICE.CLK"/>
<direct name="CE" input="SLICEM.CE" output="COMMON_SLICE.CE"/>
<direct name="SR" input="SLICEM.SR" output="COMMON_SLICE.SR"/>
<!-- WA7 and WA8 -->
<direct name="WA7" input="SLICEM.CX" output="SLICEM_MODES.WA7">
<metadata>
<meta name="fasm_mux">
SLICEM.CX = WA7USED
</meta>
</metadata>
</direct>
<direct name="WA8" input="SLICEM.BX" output="SLICEM_MODES.WA8">
<metadata>
<meta name="fasm_mux">
SLICEM.BX = WA8USED
</meta>
</metadata>
</direct>
</interconnect>
<metadata>
<meta name="type">block</meta>
<meta name="subtype">tile</meta>
</metadata>
</pb_type>
Model XML¶
<models xmlns:xi="http://www.w3.org/2001/XInclude">
<xi:include href="../common_slice/common_slice.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../common_slice/common_lut_and_f78mux.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../common_slice/muxes/f7amux/f7amux.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../common_slice/muxes/f7bmux/f7bmux.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../common_slice/muxes/f8mux/f8mux.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="Ndram/a_dram.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="Ndram/b_dram.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="Ndram/c_dram.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="Ndram/d_dram.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="dram_2_output_stub.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="dram_4_output_stub.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="dram_8_output_stub.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="di64_stub.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="srl/srlc32e_vpr.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="srl/srlc16e_vpr.model.xml" xpointer="xpointer(models/child::node())" />
</models>