symbiflow-arch-defs
symbiflow-arch-defs

bram

Physical Block XML

<!-- vim: set ai sw=1 ts=1 sta et: -->

<!--
Block RAM in 7 series is 36kbbit split into two 18kbit sections.
The Block RAM is "true dual port".
There are both Latches (first) and Registers (second) on the output (why!?)

The RAM has extra bits that can be used for parity (DIP / DOP).

This is the top level site model.  Because the 3 sites with the BRAM are
affected by the BRAM mode, each site cannot be handled independently.  For this
reason, BRAM tiles use a "fused sites" mode to accomidate the cross site logic.

  -->
<pb_type name="BRAM" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
 <!-- RAMBFIFO36E1 site pins -->
 <input  name="RAMB36_Y0_WEBWEU"         num_pins="8"  />
 <input  name="RAMB36_Y0_WEBWEL"         num_pins="8"  />
 <input  name="RAMB36_Y0_WEAU"           num_pins="4"  />
 <input  name="RAMB36_Y0_WEAL"           num_pins="4"  />

 <input  name="RAMB36_Y0_TSTWROS"        num_pins="13" />
 <input  name="RAMB36_Y0_TSTWRCNTOFF"    num_pins="1"  />
 <input  name="RAMB36_Y0_TSTRDOS"        num_pins="13" />
 <input  name="RAMB36_Y0_TSTRDCNTOFF"    num_pins="1"  />
 <input  name="RAMB36_Y0_TSTOFF"         num_pins="1"  />
 <input  name="RAMB36_Y0_TSTIN"          num_pins="5"  />
 <input  name="RAMB36_Y0_TSTFLAGIN"      num_pins="1"  />
 <input  name="RAMB36_Y0_TSTCNT"         num_pins="13" />
 <input  name="RAMB36_Y0_TSTBRAMRST"     num_pins="1"  />

 <input  name="RAMB36_Y0_RSTREGBU"       num_pins="1"  />
 <input  name="RAMB36_Y0_RSTREGBL"       num_pins="1"  />
 <input  name="RAMB36_Y0_RSTREGARSTREGU" num_pins="1"  />
 <input  name="RAMB36_Y0_RSTREGARSTREGL" num_pins="1"  />
 <input  name="RAMB36_Y0_RSTRAMBU"       num_pins="1"  />
 <input  name="RAMB36_Y0_RSTRAMBL"       num_pins="1"  />
 <input  name="RAMB36_Y0_RSTRAMARSTRAMU" num_pins="1"  />
 <input  name="RAMB36_Y0_RSTRAMARSTRAMLRST" num_pins="1" />

 <input  name="RAMB36_Y0_REGCLKBU"       num_pins="1"  />
 <input  name="RAMB36_Y0_REGCLKBL"       num_pins="1"  />
 <input  name="RAMB36_Y0_REGCLKARDRCLKU" num_pins="1"  />
 <input  name="RAMB36_Y0_REGCLKARDRCLKL" num_pins="1"  />
 <input  name="RAMB36_Y0_REGCEBU"        num_pins="1"  />
 <input  name="RAMB36_Y0_REGCEBL"        num_pins="1"  />
 <input  name="RAMB36_Y0_REGCEAREGCEU"   num_pins="1"  />
 <input  name="RAMB36_Y0_REGCEAREGCEL"   num_pins="1"  />

 <input  name="RAMB36_Y0_INJECTDBITERR"  num_pins="1"  />
 <input  name="RAMB36_Y0_INJECTSBITERR"  num_pins="1"  />

 <input  name="RAMB36_Y0_ENBWRENU"       num_pins="1"  />
 <input  name="RAMB36_Y0_ENBWRENL"       num_pins="1"  />
 <input  name="RAMB36_Y0_ENARDENU"       num_pins="1"  />
 <input  name="RAMB36_Y0_ENARDENL"       num_pins="1"  />
 <input  name="RAMB36_Y0_DIPBDIP"        num_pins="4"  />
 <input  name="RAMB36_Y0_DIPADIP"        num_pins="4"  />
 <input  name="RAMB36_Y0_DIBDI"          num_pins="32" />
 <input  name="RAMB36_Y0_DIADI"          num_pins="32" />

 <clock  name="RAMB36_Y0_CLKBWRCLKU"     num_pins="1"  />
 <clock  name="RAMB36_Y0_CLKBWRCLKL"     num_pins="1"  />
 <clock  name="RAMB36_Y0_CLKARDCLKU"     num_pins="1"  />
 <clock  name="RAMB36_Y0_CLKARDCLKL"     num_pins="1"  />

 <input  name="RAMB36_Y0_CASCADEINA"     num_pins="1"  />
 <input  name="RAMB36_Y0_CASCADEINB"     num_pins="1"  />

 <input  name="RAMB36_Y0_ADDRBWRADDRU"   num_pins="15" />
 <input  name="RAMB36_Y0_ADDRBWRADDRL"   num_pins="16" />

 <input  name="RAMB36_Y0_ADDRARDADDRU"   num_pins="15" />
 <input  name="RAMB36_Y0_ADDRARDADDRL"   num_pins="16" />

 <output name="RAMB36_Y0_WRERR"          num_pins="1"  />
 <output name="RAMB36_Y0_WRCOUNT"        num_pins="13" />

 <output name="RAMB36_Y0_TSTOUT"         num_pins="5"  />

 <output name="RAMB36_Y0_SBITERR"        num_pins="1"  />

 <output name="RAMB36_Y0_RDERR"          num_pins="1"  />
 <output name="RAMB36_Y0_RDCOUNT"        num_pins="13" />

 <output name="RAMB36_Y0_FULL"           num_pins="1"  />
 <output name="RAMB36_Y0_EMPTY"          num_pins="1"  />

 <output name="RAMB36_Y0_ECCPARITY"      num_pins="8"  />

 <output name="RAMB36_Y0_DOPBDOP"        num_pins="4"  />
 <output name="RAMB36_Y0_DOPADOP"        num_pins="4"  />

 <output name="RAMB36_Y0_DOBDO"          num_pins="32" />
 <output name="RAMB36_Y0_DOADO"          num_pins="32" />

 <output name="RAMB36_Y0_DBITERR"        num_pins="1"  />

 <output name="RAMB36_Y0_CASCADEOUTA"    num_pins="1"  />
 <output name="RAMB36_Y0_CASCADEOUTB"    num_pins="1"  />

 <output name="RAMB36_Y0_ALMOSTFULL"     num_pins="1"  />
 <output name="RAMB36_Y0_ALMOSTEMPTY"    num_pins="1"  />

 <!-- FIFO18E1 site pins -->
 <input  name="RAMB18_Y0_WREN"          num_pins="1"  />
 <input  name="RAMB18_Y0_WRCLK"         num_pins="1"  />
 <input  name="RAMB18_Y0_WEBWE"         num_pins="8"  />
 <input  name="RAMB18_Y0_WEA"           num_pins="4"  />

 <input  name="RAMB18_Y0_RSTREGB"       num_pins="1"  />
 <input  name="RAMB18_Y0_RSTREG"        num_pins="1"  />
 <input  name="RAMB18_Y0_RSTRAMB"       num_pins="1"  />
 <input  name="RAMB18_Y0_RST"           num_pins="1"  />

 <input  name="RAMB18_Y0_REGCLKB"       num_pins="1"  />
 <input  name="RAMB18_Y0_REGCEB"        num_pins="1"  />
 <input  name="RAMB18_Y0_REGCE"         num_pins="1"  />
 <input  name="RAMB18_Y0_RDRCLK"        num_pins="1"  />
 <input  name="RAMB18_Y0_RDEN"          num_pins="1"  />
 <input  name="RAMB18_Y0_RDCLK"         num_pins="1"  />

 <input  name="RAMB18_Y0_DIPBDIP"       num_pins="2"  />
 <input  name="RAMB18_Y0_DIPADIP"       num_pins="2"  />
 <input  name="RAMB18_Y0_DIBDI"         num_pins="16" />
 <input  name="RAMB18_Y0_DIADI"         num_pins="16" />

 <input  name="RAMB18_Y0_ADDRARDADDR"   num_pins="14" />
 <input  name="RAMB18_Y0_ADDRBWRADDR"   num_pins="14" />
 <input  name="RAMB18_Y0_ADDRATIEHIGH"  num_pins="2"  />
 <input  name="RAMB18_Y0_ADDRBTIEHIGH"  num_pins="2"  />

 <output name="RAMB18_Y0_WRERR"         num_pins="1"  />
 <output name="RAMB18_Y0_WRCOUNT"       num_pins="12" />
 <output name="RAMB18_Y0_RDERR"         num_pins="1"  />
 <output name="RAMB18_Y0_RDCOUNT"       num_pins="12" />
 <output name="RAMB18_Y0_FULL"          num_pins="1"  />
 <output name="RAMB18_Y0_EMPTY"         num_pins="1"  />
 <output name="RAMB18_Y0_DOP"           num_pins="4"  />
 <output name="RAMB18_Y0_DO"            num_pins="32" />
 <output name="RAMB18_Y0_ALMOSTFULL"    num_pins="1"  />
 <output name="RAMB18_Y0_ALMOSTEMPTY"   num_pins="1"  />

 <!-- RAMB18E1 site pins -->
 <input  name="RAMB18_Y1_ENBWREN"       num_pins="1"  />
 <input  name="RAMB18_Y1_CLKBWRCLK"     num_pins="1"  />
 <input  name="RAMB18_Y1_WEBWE"         num_pins="8"  />
 <input  name="RAMB18_Y1_WEA"           num_pins="4"  />

 <input  name="RAMB18_Y1_RSTREGB"       num_pins="1"  />
 <input  name="RAMB18_Y1_RSTREGARSTREG" num_pins="1"  />
 <input  name="RAMB18_Y1_RSTRAMB"       num_pins="1"  />
 <input  name="RAMB18_Y1_RSTRAMARSTRAM" num_pins="1"  />

 <input  name="RAMB18_Y1_REGCLKB"       num_pins="1"  />
 <input  name="RAMB18_Y1_REGCEB"        num_pins="1"  />
 <input  name="RAMB18_Y1_REGCEAREGCE"   num_pins="1"  />
 <input  name="RAMB18_Y1_REGCLKARDRCLK" num_pins="1"  />
 <input  name="RAMB18_Y1_ENARDEN"       num_pins="1"  />
 <input  name="RAMB18_Y1_CLKARDCLK"     num_pins="1"  />

 <input  name="RAMB18_Y1_DIPBDIP"       num_pins="2"  />
 <input  name="RAMB18_Y1_DIPADIP"       num_pins="2"  />
 <input  name="RAMB18_Y1_DIBDI"         num_pins="16" />
 <input  name="RAMB18_Y1_DIADI"         num_pins="16" />

 <input  name="RAMB18_Y1_ADDRARDADDR"   num_pins="14" />
 <input  name="RAMB18_Y1_ADDRBWRADDR"   num_pins="14" />
 <input  name="RAMB18_Y1_ADDRATIEHIGH"  num_pins="2"  />
 <input  name="RAMB18_Y1_ADDRBTIEHIGH"  num_pins="2"  />

 <output name="RAMB18_Y1_WRERR"         num_pins="1"  />
 <output name="RAMB18_Y1_WRCOUNT"       num_pins="12" />
 <output name="RAMB18_Y1_RDERR"         num_pins="1"  />
 <output name="RAMB18_Y1_RDCOUNT"       num_pins="12" />
 <output name="RAMB18_Y1_FULL"          num_pins="1"  />
 <output name="RAMB18_Y1_EMPTY"         num_pins="1"  />
 <output name="RAMB18_Y1_DOPADOP"       num_pins="2"  />
 <output name="RAMB18_Y1_DOPBDOP"       num_pins="2"  />
 <output name="RAMB18_Y1_DOADO"         num_pins="16" />
 <output name="RAMB18_Y1_DOBDO"         num_pins="16" />
 <output name="RAMB18_Y1_ALMOSTFULL"    num_pins="1"  />
 <output name="RAMB18_Y1_ALMOSTEMPTY"   num_pins="1"  />

 <mode name="BRAM36">
  <xi:include href="rambfifo36e1.pb_type.xml" />
  <interconnect>
   <direct name="RAMB36_X0Y0_WEBWEU"            input="BRAM.RAMB36_Y0_WEBWEU"             output="RAMBFIFO36E1.WEBWEU" />
   <direct name="RAMB36_X0Y0_WEBWEL"            input="BRAM.RAMB36_Y0_WEBWEL"             output="RAMBFIFO36E1.WEBWEL" />
   <direct name="RAMB36_X0Y0_WEAU"              input="BRAM.RAMB36_Y0_WEAU"               output="RAMBFIFO36E1.WEAU" />
   <direct name="RAMB36_X0Y0_WEAL"              input="BRAM.RAMB36_Y0_WEAL"               output="RAMBFIFO36E1.WEAL" />

   <direct name="RAMB36_X0Y0_TSTWROS"           input="BRAM.RAMB36_Y0_TSTWROS"            output="RAMBFIFO36E1.TSTWROS" />
   <direct name="RAMB36_X0Y0_TSTWRCNTOFF"       input="BRAM.RAMB36_Y0_TSTWRCNTOFF"        output="RAMBFIFO36E1.TSTWRCNTOFF" />
   <direct name="RAMB36_X0Y0_TSTRDOS"           input="BRAM.RAMB36_Y0_TSTRDOS"            output="RAMBFIFO36E1.TSTRDOS" />
   <direct name="RAMB36_X0Y0_TSTRDCNTOFF"       input="BRAM.RAMB36_Y0_TSTRDCNTOFF"        output="RAMBFIFO36E1.TSTRDCNTOFF" />
   <direct name="RAMB36_X0Y0_TSTOFF"            input="BRAM.RAMB36_Y0_TSTOFF"             output="RAMBFIFO36E1.TSTOFF" />
   <direct name="RAMB36_X0Y0_TSTIN"             input="BRAM.RAMB36_Y0_TSTIN"              output="RAMBFIFO36E1.TSTIN" />
   <direct name="RAMB36_X0Y0_TSTFLAGIN"         input="BRAM.RAMB36_Y0_TSTFLAGIN"          output="RAMBFIFO36E1.TSTFLAGIN" />
   <direct name="RAMB36_X0Y0_TSTCNT"            input="BRAM.RAMB36_Y0_TSTCNT"             output="RAMBFIFO36E1.TSTCNT" />
   <direct name="RAMB36_X0Y0_TSTBRAMRST"        input="BRAM.RAMB36_Y0_TSTBRAMRST"         output="RAMBFIFO36E1.TSTBRAMRST" />

   <direct name="RAMB36_X0Y0_RSTREGBU"          input="BRAM.RAMB36_Y0_RSTREGBU"           output="RAMBFIFO36E1.RSTREGBU" />
   <direct name="RAMB36_X0Y0_RSTREGBL"          input="BRAM.RAMB36_Y0_RSTREGBL"           output="RAMBFIFO36E1.RSTREGBL" />
   <direct name="RAMB36_X0Y0_RSTREGARSTREGU"    input="BRAM.RAMB36_Y0_RSTREGARSTREGU"     output="RAMBFIFO36E1.RSTREGARSTREGU" />
   <direct name="RAMB36_X0Y0_RSTREGARSTREGL"    input="BRAM.RAMB36_Y0_RSTREGARSTREGL"     output="RAMBFIFO36E1.RSTREGARSTREGL" />
   <direct name="RAMB36_X0Y0_RSTRAMBU"          input="BRAM.RAMB36_Y0_RSTRAMBU"           output="RAMBFIFO36E1.RSTRAMBU" />
   <direct name="RAMB36_X0Y0_RSTRAMBL"          input="BRAM.RAMB36_Y0_RSTRAMBL"           output="RAMBFIFO36E1.RSTRAMBL" />
   <direct name="RAMB36_X0Y0_RSTRAMARSTRAMU"    input="BRAM.RAMB36_Y0_RSTRAMARSTRAMU"     output="RAMBFIFO36E1.RSTRAMARSTRAMU" />
   <direct name="RAMB36_X0Y0_RSTRAMARSTRAMLRST" input="BRAM.RAMB36_Y0_RSTRAMARSTRAMLRST"  output="RAMBFIFO36E1.RSTRAMARSTRAMLRST" />

   <direct name="RAMB36_X0Y0_REGCLKBU"          input="BRAM.RAMB36_Y0_REGCLKBU"           output="RAMBFIFO36E1.REGCLKBU" />
   <direct name="RAMB36_X0Y0_REGCLKBL"          input="BRAM.RAMB36_Y0_REGCLKBL"           output="RAMBFIFO36E1.REGCLKBL" />
   <direct name="RAMB36_X0Y0_REGCLKARDRCLKU"    input="BRAM.RAMB36_Y0_REGCLKARDRCLKU"     output="RAMBFIFO36E1.REGCLKARDRCLKU" />
   <direct name="RAMB36_X0Y0_REGCLKARDRCLKL"    input="BRAM.RAMB36_Y0_REGCLKARDRCLKL"     output="RAMBFIFO36E1.REGCLKARDRCLKL" />
   <direct name="RAMB36_X0Y0_REGCEBU"           input="BRAM.RAMB36_Y0_REGCEBU"            output="RAMBFIFO36E1.REGCEBU" />
   <direct name="RAMB36_X0Y0_REGCEBL"           input="BRAM.RAMB36_Y0_REGCEBL"            output="RAMBFIFO36E1.REGCEBL" />
   <direct name="RAMB36_X0Y0_REGCEAREGCEU"      input="BRAM.RAMB36_Y0_REGCEAREGCEU"       output="RAMBFIFO36E1.REGCEAREGCEU" />
   <direct name="RAMB36_X0Y0_REGCEAREGCEL"      input="BRAM.RAMB36_Y0_REGCEAREGCEL"       output="RAMBFIFO36E1.REGCEAREGCEL" />

   <direct name="RAMB36_X0Y0_INJECTDBITERR"     input="BRAM.RAMB36_Y0_INJECTDBITERR"      output="RAMBFIFO36E1.INJECTDBITERR" />
   <direct name="RAMB36_X0Y0_INJECTSBITERR"     input="BRAM.RAMB36_Y0_INJECTSBITERR"      output="RAMBFIFO36E1.INJECTSBITERR" />

   <direct name="RAMB36_X0Y0_ENBWRENU"          input="BRAM.RAMB36_Y0_ENBWRENU"           output="RAMBFIFO36E1.ENBWRENU" />
   <direct name="RAMB36_X0Y0_ENBWRENL"          input="BRAM.RAMB36_Y0_ENBWRENL"           output="RAMBFIFO36E1.ENBWRENL" />
   <direct name="RAMB36_X0Y0_ENARDENU"          input="BRAM.RAMB36_Y0_ENARDENU"           output="RAMBFIFO36E1.ENARDENU" />
   <direct name="RAMB36_X0Y0_ENARDENL"          input="BRAM.RAMB36_Y0_ENARDENL"           output="RAMBFIFO36E1.ENARDENL" />
   <direct name="RAMB36_X0Y0_DIPBDIP"           input="BRAM.RAMB36_Y0_DIPBDIP"            output="RAMBFIFO36E1.DIPBDIP" />
   <direct name="RAMB36_X0Y0_DIPADIP"           input="BRAM.RAMB36_Y0_DIPADIP"            output="RAMBFIFO36E1.DIPADIP" />
   <direct name="RAMB36_X0Y0_DIBDI"             input="BRAM.RAMB36_Y0_DIBDI"              output="RAMBFIFO36E1.DIBDI" />
   <direct name="RAMB36_X0Y0_DIADI"             input="BRAM.RAMB36_Y0_DIADI"              output="RAMBFIFO36E1.DIADI" />

   <direct name="RAMB36_X0Y0_CLKBWRCLKU"        input="BRAM.RAMB36_Y0_CLKBWRCLKU"         output="RAMBFIFO36E1.CLKBWRCLKU" />
   <direct name="RAMB36_X0Y0_CLKBWRCLKL"        input="BRAM.RAMB36_Y0_CLKBWRCLKL"         output="RAMBFIFO36E1.CLKBWRCLKL" />
   <direct name="RAMB36_X0Y0_CLKARDCLKU"        input="BRAM.RAMB36_Y0_CLKARDCLKU"         output="RAMBFIFO36E1.CLKARDCLKU" />
   <direct name="RAMB36_X0Y0_CLKARDCLKL"        input="BRAM.RAMB36_Y0_CLKARDCLKL"         output="RAMBFIFO36E1.CLKARDCLKL" />

   <direct name="RAMB36_X0Y0_CASCADEINA"        input="BRAM.RAMB36_Y0_CASCADEINA"         output="RAMBFIFO36E1.CASCADEINA" />
   <direct name="RAMB36_X0Y0_CASCADEINB"        input="BRAM.RAMB36_Y0_CASCADEINB"         output="RAMBFIFO36E1.CASCADEINB" />

   <direct name="RAMB36_X0Y0_ADDRBWRADDRU"      input="BRAM.RAMB36_Y0_ADDRBWRADDRU"       output="RAMBFIFO36E1.ADDRBWRADDRU" />
   <direct name="RAMB36_X0Y0_ADDRBWRADDRL"      input="BRAM.RAMB36_Y0_ADDRBWRADDRL"       output="RAMBFIFO36E1.ADDRBWRADDRL" />

   <direct name="RAMB36_X0Y0_ADDRARDADDRU"      input="BRAM.RAMB36_Y0_ADDRARDADDRU"       output="RAMBFIFO36E1.ADDRARDADDRU" />
   <direct name="RAMB36_X0Y0_ADDRARDADDRL"      input="BRAM.RAMB36_Y0_ADDRARDADDRL"       output="RAMBFIFO36E1.ADDRARDADDRL" />

   <direct name="RAMB36_X0Y0_WRERR"             input="RAMBFIFO36E1.WRERR"                output="BRAM.RAMB36_Y0_WRERR" />
   <direct name="RAMB36_X0Y0_WRCOUNT"           input="RAMBFIFO36E1.WRCOUNT"              output="BRAM.RAMB36_Y0_WRCOUNT" />

   <direct name="RAMB36_X0Y0_TSTOUT"            input="RAMBFIFO36E1.TSTOUT"               output="BRAM.RAMB36_Y0_TSTOUT" />

   <direct name="RAMB36_X0Y0_SBITERR"           input="RAMBFIFO36E1.SBITERR"              output="BRAM.RAMB36_Y0_SBITERR" />

   <direct name="RAMB36_X0Y0_RDERR"             input="RAMBFIFO36E1.RDERR"                output="BRAM.RAMB36_Y0_RDERR" />
   <direct name="RAMB36_X0Y0_RDCOUNT"           input="RAMBFIFO36E1.RDCOUNT"              output="BRAM.RAMB36_Y0_RDCOUNT" />

   <direct name="RAMB36_X0Y0_FULL"              input="RAMBFIFO36E1.FULL"                 output="BRAM.RAMB36_Y0_FULL" />
   <direct name="RAMB36_X0Y0_EMPTY"             input="RAMBFIFO36E1.EMPTY"                output="BRAM.RAMB36_Y0_EMPTY" />

   <direct name="RAMB36_X0Y0_ECCPARITY"         input="RAMBFIFO36E1.ECCPARITY"            output="BRAM.RAMB36_Y0_ECCPARITY" />

   <direct name="RAMB36_X0Y0_DOPBDOP"           input="RAMBFIFO36E1.DOPBDOP"              output="BRAM.RAMB36_Y0_DOPBDOP" />
   <direct name="RAMB36_X0Y0_DOPADOP"           input="RAMBFIFO36E1.DOPADOP"              output="BRAM.RAMB36_Y0_DOPADOP" />

   <direct name="RAMB36_X0Y0_DOBDO"             input="RAMBFIFO36E1.DOBDO"                output="BRAM.RAMB36_Y0_DOBDO" />
   <direct name="RAMB36_X0Y0_DOADO"             input="RAMBFIFO36E1.DOADO"                output="BRAM.RAMB36_Y0_DOADO" />

   <direct name="RAMB36_X0Y0_DBITERR"           input="RAMBFIFO36E1.DBITERR"              output="BRAM.RAMB36_Y0_DBITERR" />

   <direct name="RAMB36_X0Y0_CASCADEOUTA"       input="RAMBFIFO36E1.CASCADEOUTA"          output="BRAM.RAMB36_Y0_CASCADEOUTA" />
   <direct name="RAMB36_X0Y0_CASCADEOUTB"       input="RAMBFIFO36E1.CASCADEOUTB"          output="BRAM.RAMB36_Y0_CASCADEOUTB" />

   <direct name="RAMB36_X0Y0_ALMOSTFULL"        input="RAMBFIFO36E1.ALMOSTFULL"           output="BRAM.RAMB36_Y0_ALMOSTFULL" />
   <direct name="RAMB36_X0Y0_ALMOSTEMPTY"       input="RAMBFIFO36E1.ALMOSTEMPTY"          output="BRAM.RAMB36_Y0_ALMOSTEMPTY" />
  </interconnect>
 </mode>
 <mode name="2xBRAM18">
  <pb_type name="RAMB18E1_Y0" num_pb="1">
   <clock  name="CLKARDCLK"     num_pins="1"  />
    <input  name="REGCEAREGCE"   num_pins="1"  />
    <input  name="REGCLKARDRCLK" num_pins="1"  />
    <input  name="ENARDEN"       num_pins="1"  />
    <input  name="RSTRAMARSTRAM" num_pins="1"  />
    <input  name="RSTREGARSTREG" num_pins="1"  />
    <input  name="ADDRATIEHIGH"  num_pins="2"  />
    <input  name="ADDRARDADDR"   num_pins="14" />
    <input  name="DIADI"         num_pins="16" />
    <input  name="DIPADIP"       num_pins="2"  />
    <input  name="WEA"           num_pins="4"  />
    <output name="DOADO"         num_pins="16" />
    <output name="DOPADOP"       num_pins="2"  />

    <clock  name="CLKBWRCLK"     num_pins="1"  />
    <input  name="ENBWREN"       num_pins="1"  />
    <input  name="REGCEB"        num_pins="1"  />
    <input  name="REGCLKB"       num_pins="1"  />
    <input  name="RSTRAMB"       num_pins="1"  />
    <input  name="RSTREGB"       num_pins="1"  />
    <input  name="ADDRBTIEHIGH"  num_pins="2"  />
    <input  name="ADDRBWRADDR"   num_pins="14" />
    <input  name="DIBDI"         num_pins="16" />
    <input  name="DIPBDIP"       num_pins="2"  />
    <input  name="WEBWE"         num_pins="8"  />
    <output name="DOBDO"         num_pins="16" />
    <output name="DOPBDOP"       num_pins="2"  />

    <mode name="Unused BRAM">
     <interconnect />
    </mode>
    <mode name="RAMB18_Y0">
     <pb_type name="RAMB18E1_Y0_IN" num_pb="1" blif_model=".subckt RAMB18E1_VPR">
      <xi:include href="ramb18e1.pb_type.xml" xpointer="xpointer(pb_type/child::node()[local-name()!='metadata'])" />
      <metadata>
       <!-- As there is a difference in how BRAM get translated into the bitstream depending on
            the operational mode, we need to add specific READ_WIDTH_A parameters that correspond
            to the site location of the RAMB.
            Further explanation can be found in the RAMB18E1 techmap -->
       <xi:include href="ramb18e1.pb_type.xml" xpointer="xpointer(pb_type/metadata/meta[not(@name='fasm_params')])" />
       <meta name="fasm_params">
        <xi:include href="ramb18e1.pb_type.xml" xpointer="xpointer(pb_type/metadata/meta[attribute::name='fasm_params']/child::node())" />
        READ_WIDTH_A_1  = Y0_READ_WIDTH_A_1
        READ_WIDTH_A_18 = Y0_READ_WIDTH_A_18
       </meta>
       <meta name="fasm_prefix">RAMB18_Y0</meta>
      </metadata>
     </pb_type>
     <interconnect>
      <direct name="WREN"             input="RAMB18E1_Y0.ENBWREN"       output="RAMB18E1_Y0_IN.ENBWREN" />
      <direct name="WRCLK"            input="RAMB18E1_Y0.CLKBWRCLK"     output="RAMB18E1_Y0_IN.CLKBWRCLK" />
      <direct name="WEBWE"            input="RAMB18E1_Y0.WEBWE"         output="RAMB18E1_Y0_IN.WEBWE" />
      <direct name="WEA"              input="RAMB18E1_Y0.WEA"           output="RAMB18E1_Y0_IN.WEA" />

      <direct name="RSTREGB"          input="RAMB18E1_Y0.RSTREGB"       output="RAMB18E1_Y0_IN.RSTREGB" />
      <direct name="RSTREG"           input="RAMB18E1_Y0.RSTREGARSTREG" output="RAMB18E1_Y0_IN.RSTREGARSTREG" />
      <direct name="RSTRAMB"          input="RAMB18E1_Y0.RSTRAMB"       output="RAMB18E1_Y0_IN.RSTRAMB" />
      <direct name="RST"              input="RAMB18E1_Y0.RSTRAMARSTRAM" output="RAMB18E1_Y0_IN.RSTRAMARSTRAM" />

      <direct name="REGCLKB"          input="RAMB18E1_Y0.REGCLKB"       output="RAMB18E1_Y0_IN.REGCLKB" />
      <direct name="REGCEB"           input="RAMB18E1_Y0.REGCEB"        output="RAMB18E1_Y0_IN.REGCEB" />
      <direct name="REGCE"            input="RAMB18E1_Y0.REGCEAREGCE"   output="RAMB18E1_Y0_IN.REGCEAREGCE" />
      <direct name="RDRCLK"           input="RAMB18E1_Y0.REGCLKARDRCLK" output="RAMB18E1_Y0_IN.REGCLKARDRCLK" />
      <direct name="RDEN"             input="RAMB18E1_Y0.ENARDEN"       output="RAMB18E1_Y0_IN.ENARDEN" />
      <direct name="RDCLK"            input="RAMB18E1_Y0.CLKARDCLK"     output="RAMB18E1_Y0_IN.CLKARDCLK" />

      <direct name="DIPBDIP"          input="RAMB18E1_Y0.DIPBDIP"       output="RAMB18E1_Y0_IN.DIPBDIP" />
      <direct name="DIPADIP"          input="RAMB18E1_Y0.DIPADIP"       output="RAMB18E1_Y0_IN.DIPADIP" />
      <direct name="DIBDI"            input="RAMB18E1_Y0.DIBDI"         output="RAMB18E1_Y0_IN.DIBDI" />
      <direct name="DIADI"            input="RAMB18E1_Y0.DIADI"         output="RAMB18E1_Y0_IN.DIADI" />

      <direct name="ADDRATIEHIGH"     input="RAMB18E1_Y0.ADDRATIEHIGH"  output="RAMB18E1_Y0_IN.ADDRATIEHIGH" />
      <direct name="ADDRARDADDR"      input="RAMB18E1_Y0.ADDRARDADDR"   output="RAMB18E1_Y0_IN.ADDRARDADDR" />
      <direct name="ADDRBTIEHIGH"     input="RAMB18E1_Y0.ADDRBTIEHIGH"  output="RAMB18E1_Y0_IN.ADDRBTIEHIGH" />
      <direct name="ADDRBWRADDR"      input="RAMB18E1_Y0.ADDRBWRADDR"   output="RAMB18E1_Y0_IN.ADDRBWRADDR" />

      <direct name="DOBDOP"           input="RAMB18E1_Y0_IN.DOPBDOP"    output="RAMB18E1_Y0.DOPBDOP" />
      <direct name="DOADOP"           input="RAMB18E1_Y0_IN.DOPADOP"    output="RAMB18E1_Y0.DOPADOP" />
      <direct name="DOBDO"            input="RAMB18E1_Y0_IN.DOBDO"      output="RAMB18E1_Y0.DOBDO" />
      <direct name="DOADO"            input="RAMB18E1_Y0_IN.DOADO"      output="RAMB18E1_Y0.DOADO" />
     </interconnect>
     <metadata>
      <!-- These features are emitted when RAMB18_Y0 is used in RAM mode. -->
      <meta name="fasm_features">
       ZALMOST_EMPTY_OFFSET[12:0]=13'b1111111111111
       ZALMOST_FULL_OFFSET[12:0]=13'b1111111111111
      </meta>
     </metadata>
    </mode>
  </pb_type>
  <pb_type name="RAMB18E1_Y1" num_pb="1" blif_model=".subckt RAMB18E1_VPR">
   <xi:include href="ramb18e1.pb_type.xml" xpointer="xpointer(pb_type/child::node()[local-name()!='metadata'])" />
   <metadata>
     <!-- As there is a difference in how BRAM get translated into the bitstream depending on
          the operational mode, we need to add specific READ_WIDTH_A parameters that correspond
          to the site location of the RAMB.
          Further explanation can be found in the RAMB18E1 techmap -->
     <xi:include href="ramb18e1.pb_type.xml" xpointer="xpointer(pb_type/metadata/meta[not(@name='fasm_params')])" />
     <meta name="fasm_params">
      <xi:include href="ramb18e1.pb_type.xml" xpointer="xpointer(pb_type/metadata/meta[@name='fasm_params']/child::node())" />
      READ_WIDTH_A_1  = Y1_READ_WIDTH_A_1
      READ_WIDTH_A_18 = Y1_READ_WIDTH_A_18
     </meta>
     <meta name="fasm_prefix">RAMB18_Y1</meta>
   </metadata>
  </pb_type>
  <interconnect>
   <!-- Y0 should point to a rambfifo18e1 model, not ramb18e1 model. -->
   <direct name="RAMB18_X0Y0_WREN"             input="BRAM.RAMB18_Y0_WREN"              output="RAMB18E1_Y0.ENBWREN" />
   <direct name="RAMB18_X0Y0_WRCLK"            input="BRAM.RAMB18_Y0_WRCLK"             output="RAMB18E1_Y0.CLKBWRCLK" />
   <direct name="RAMB18_X0Y0_WEBWE"            input="BRAM.RAMB18_Y0_WEBWE"             output="RAMB18E1_Y0.WEBWE" />
   <direct name="RAMB18_X0Y0_WEA"              input="BRAM.RAMB18_Y0_WEA"               output="RAMB18E1_Y0.WEA" />

   <direct name="RAMB18_X0Y0_RSTREGB"          input="BRAM.RAMB18_Y0_RSTREGB"           output="RAMB18E1_Y0.RSTREGB" />
   <direct name="RAMB18_X0Y0_RSTREG"           input="BRAM.RAMB18_Y0_RSTREG"            output="RAMB18E1_Y0.RSTREGARSTREG" />
   <direct name="RAMB18_X0Y0_RSTRAMB"          input="BRAM.RAMB18_Y0_RSTRAMB"           output="RAMB18E1_Y0.RSTRAMB" />
   <direct name="RAMB18_X0Y0_RST"              input="BRAM.RAMB18_Y0_RST"               output="RAMB18E1_Y0.RSTRAMARSTRAM" />

   <direct name="RAMB18_X0Y0_REGCLKB"          input="BRAM.RAMB18_Y0_REGCLKB"           output="RAMB18E1_Y0.REGCLKB" />
   <direct name="RAMB18_X0Y0_REGCEB"           input="BRAM.RAMB18_Y0_REGCEB"            output="RAMB18E1_Y0.REGCEB" />
   <direct name="RAMB18_X0Y0_REGCE"            input="BRAM.RAMB18_Y0_REGCE"             output="RAMB18E1_Y0.REGCEAREGCE" />
   <direct name="RAMB18_X0Y0_RDRCLK"           input="BRAM.RAMB18_Y0_RDRCLK"            output="RAMB18E1_Y0.REGCLKARDRCLK" />
   <direct name="RAMB18_X0Y0_RDEN"             input="BRAM.RAMB18_Y0_RDEN"              output="RAMB18E1_Y0.ENARDEN" />
   <direct name="RAMB18_X0Y0_RDCLK"            input="BRAM.RAMB18_Y0_RDCLK"             output="RAMB18E1_Y0.CLKARDCLK" />

   <direct name="RAMB18_X0Y0_DIPBDIP"          input="BRAM.RAMB18_Y0_DIPBDIP"           output="RAMB18E1_Y0.DIPBDIP" />
   <direct name="RAMB18_X0Y0_DIPADIP"          input="BRAM.RAMB18_Y0_DIPADIP"           output="RAMB18E1_Y0.DIPADIP" />
   <direct name="RAMB18_X0Y0_DIBDI"            input="BRAM.RAMB18_Y0_DIBDI"             output="RAMB18E1_Y0.DIBDI" />
   <direct name="RAMB18_X0Y0_DIADI"            input="BRAM.RAMB18_Y0_DIADI"             output="RAMB18E1_Y0.DIADI" />

   <direct name="RAMB18_X0Y0_ADDRATIEHIGH"     input="BRAM.RAMB18_Y0_ADDRATIEHIGH"      output="RAMB18E1_Y0.ADDRATIEHIGH" />
   <direct name="RAMB18_X0Y0_ADDRARDADDR"      input="BRAM.RAMB18_Y0_ADDRARDADDR"       output="RAMB18E1_Y0.ADDRARDADDR" />
   <direct name="RAMB18_X0Y0_ADDRBTIEHIGH"     input="BRAM.RAMB18_Y0_ADDRBTIEHIGH"      output="RAMB18E1_Y0.ADDRBTIEHIGH" />
   <direct name="RAMB18_X0Y0_ADDRBWRADDR"      input="BRAM.RAMB18_Y0_ADDRBWRADDR"       output="RAMB18E1_Y0.ADDRBWRADDR" />

   <direct name="RAMB18_X0Y0_DOBDOP"           input="RAMB18E1_Y0.DOPBDOP"              output="BRAM.RAMB18_Y0_DOP[3:2]" />
   <direct name="RAMB18_X0Y0_DOADOP"           input="RAMB18E1_Y0.DOPADOP"              output="BRAM.RAMB18_Y0_DOP[1:0]" />
   <direct name="RAMB18_X0Y0_DOBDO"            input="RAMB18E1_Y0.DOBDO"                output="BRAM.RAMB18_Y0_DO[31:16]" />
   <direct name="RAMB18_X0Y0_DOADO"            input="RAMB18E1_Y0.DOADO"                output="BRAM.RAMB18_Y0_DO[15:0]" />

   <direct name="RAMB18_X0Y1_ENBWREN"          input="BRAM.RAMB18_Y1_ENBWREN"           output="RAMB18E1_Y1.ENBWREN" />
   <direct name="RAMB18_X0Y1_CLKBWRCLK"        input="BRAM.RAMB18_Y1_CLKBWRCLK"         output="RAMB18E1_Y1.CLKBWRCLK" />
   <direct name="RAMB18_X0Y1_WEBWE"            input="BRAM.RAMB18_Y1_WEBWE"             output="RAMB18E1_Y1.WEBWE" />
   <direct name="RAMB18_X0Y1_WEA"              input="BRAM.RAMB18_Y1_WEA"               output="RAMB18E1_Y1.WEA" />

   <direct name="RAMB18_X0Y1_RSTREGB"          input="BRAM.RAMB18_Y1_RSTREGB"           output="RAMB18E1_Y1.RSTREGB" />
   <direct name="RAMB18_X0Y1_RSTREGARSTREG"    input="BRAM.RAMB18_Y1_RSTREGARSTREG"     output="RAMB18E1_Y1.RSTREGARSTREG" />
   <direct name="RAMB18_X0Y1_RSTRAMB"          input="BRAM.RAMB18_Y1_RSTRAMB"           output="RAMB18E1_Y1.RSTRAMB" />
   <direct name="RAMB18_X0Y1_RSTRAMARSTRAM"    input="BRAM.RAMB18_Y1_RSTRAMARSTRAM"     output="RAMB18E1_Y1.RSTRAMARSTRAM" />

   <direct name="RAMB18_X0Y1_REGCLKB"          input="BRAM.RAMB18_Y1_REGCLKB"           output="RAMB18E1_Y1.REGCLKB" />
   <direct name="RAMB18_X0Y1_REGCEB"           input="BRAM.RAMB18_Y1_REGCEB"            output="RAMB18E1_Y1.REGCEB" />
   <direct name="RAMB18_X0Y1_REGCEAREGCE"      input="BRAM.RAMB18_Y1_REGCEAREGCE"       output="RAMB18E1_Y1.REGCEAREGCE" />
   <direct name="RAMB18_X0Y1_REGCLKARDRCLK"    input="BRAM.RAMB18_Y1_REGCLKARDRCLK"     output="RAMB18E1_Y1.REGCLKARDRCLK" />
   <direct name="RAMB18_X0Y1_ENARDEN"          input="BRAM.RAMB18_Y1_ENARDEN"           output="RAMB18E1_Y1.ENARDEN" />
   <direct name="RAMB18_X0Y1_CLKARDCLK"        input="BRAM.RAMB18_Y1_CLKARDCLK"         output="RAMB18E1_Y1.CLKARDCLK" />

   <direct name="RAMB18_X0Y1_DIPBDIP"          input="BRAM.RAMB18_Y1_DIPBDIP"           output="RAMB18E1_Y1.DIPBDIP" />
   <direct name="RAMB18_X0Y1_DIPADIP"          input="BRAM.RAMB18_Y1_DIPADIP"           output="RAMB18E1_Y1.DIPADIP" />
   <direct name="RAMB18_X0Y1_DIBDI"            input="BRAM.RAMB18_Y1_DIBDI"             output="RAMB18E1_Y1.DIBDI" />
   <direct name="RAMB18_X0Y1_DIADI"            input="BRAM.RAMB18_Y1_DIADI"             output="RAMB18E1_Y1.DIADI" />

   <direct name="RAMB18_X0Y1_ADDRATIEHIGH"     input="BRAM.RAMB18_Y1_ADDRATIEHIGH"      output="RAMB18E1_Y1.ADDRATIEHIGH" />
   <direct name="RAMB18_X0Y1_ADDRARDADDR"      input="BRAM.RAMB18_Y1_ADDRARDADDR"       output="RAMB18E1_Y1.ADDRARDADDR" />
   <direct name="RAMB18_X0Y1_ADDRBTIEHIGH"     input="BRAM.RAMB18_Y1_ADDRBTIEHIGH"      output="RAMB18E1_Y1.ADDRBTIEHIGH" />
   <direct name="RAMB18_X0Y1_ADDRBWRADDR"      input="BRAM.RAMB18_Y1_ADDRBWRADDR"       output="RAMB18E1_Y1.ADDRBWRADDR" />

   <direct name="RAMB18_X0Y1_DOPADOP"          input="RAMB18E1_Y1.DOPADOP"              output="BRAM.RAMB18_Y1_DOPADOP" />
   <direct name="RAMB18_X0Y1_DOPBDOP"          input="RAMB18E1_Y1.DOPBDOP"              output="BRAM.RAMB18_Y1_DOPBDOP" />
   <direct name="RAMB18_X0Y1_DOADO"            input="RAMB18E1_Y1.DOADO"                output="BRAM.RAMB18_Y1_DOADO" />
   <direct name="RAMB18_X0Y1_DOBDO"            input="RAMB18E1_Y1.DOBDO"                output="BRAM.RAMB18_Y1_DOBDO" />
  </interconnect>
 </mode>
 <metadata>
  <meta name="type">block</meta>
  <meta name="subtype">ignore</meta>
 </metadata>
</pb_type>

Model XML

<models xmlns:xi="http://www.w3.org/2001/XInclude">
 <xi:include href="ramb18e1.model.xml" xpointer="xpointer(models/child::node())" />
 <xi:include href="rambfifo36e1.model.xml" xpointer="xpointer(models/child::node())" />
</models>

Table Of Contents