d_dram128¶

Physical Block XML¶

<pb_type name="D_DRAM128" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
  <clock  name="CLK" num_pins="1" />
  <input  name="A"   num_pins="6" />
  <input  name="WA7" num_pins="1" />
  <input  name="DI1" num_pins="1" />
  <input  name="WE"  num_pins="1" />

  <output name="O6"  num_pins="1" />

 <mode name="128_SINGLE_PORT">
   <xi:include href="dpram64_for_ram128x1d.pb_type.xml" />
   <interconnect>
     <direct name="CLK" input="D_DRAM128.CLK" output="DPRAM64_for_RAM128X1D.CLK" />
     <direct name="A" input="D_DRAM128.A" output="DPRAM64_for_RAM128X1D.A" />
     <direct name="WA" input="D_DRAM128.A" output="DPRAM64_for_RAM128X1D.WA" />
     <direct name="WA7" input="D_DRAM128.WA7" output="DPRAM64_for_RAM128X1D.WA7" />
     <direct name="DI" input="D_DRAM128.DI1" output="DPRAM64_for_RAM128X1D.DI" />
     <direct name="WE" input="D_DRAM128.WE" output="DPRAM64_for_RAM128X1D.WE" />

     <direct name="O6" input="DPRAM64_for_RAM128X1D.O" output="D_DRAM128.O6" />
   </interconnect>
 </mode>

 <metadata>
  <meta name="fasm_prefix">DLUT</meta>
  <meta name="type">block</meta>
  <meta name="subtype">ignore</meta>
 </metadata>
</pb_type>