symbiflow-arch-defs
symbiflow-arch-defs

ram

Physical Block XML

<!-- set: ai sw=1 ts=1 sta et -->
<!-- A diagram for the iCE40 PLB "Block RAM" is shown in;
      http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf
  -->
<pb_type name="RAM" height="2" xmlns:xi="http://www.w3.org/2001/XInclude">
 <!-- Read port -->
 <output name="RDATA" num_pins="16"/>
 <input  name="RADDR"  num_pins="11"/>
 <input  name="RE"     num_pins="1"/>
 <input  name="RCLKE"  num_pins="1"/>
 <clock  name="RCLK"   num_pins="1"/>
 <!-- Write port -->
 <input  name="WDATA" num_pins="16"/>
 <input  name="MASK"  num_pins="16"/>
 <input  name="WADDR"  num_pins="11"/>
 <input  name="WE"     num_pins="1"/>
 <input  name="WCLKE"  num_pins="1"/>
 <clock  name="WCLK"   num_pins="1"/>

 <xi:include href="../../../../primitives/sb_ram/sb_ram.pb_type.xml"/>

 <interconnect>
  <direct><port type="input" name="RDATA[0]"  from="SB_RAM"/><port type="output" name="RDATA[0]" /></direct>
  <direct><port type="input" name="RDATA[1]"  from="SB_RAM"/><port type="output" name="RDATA[1]" /></direct>
  <direct><port type="input" name="RDATA[2]"  from="SB_RAM"/><port type="output" name="RDATA[2]" /></direct>
  <direct><port type="input" name="RDATA[3]"  from="SB_RAM"/><port type="output" name="RDATA[3]" /></direct>
  <direct><port type="input" name="RDATA[4]"  from="SB_RAM"/><port type="output" name="RDATA[4]" /></direct>
  <direct><port type="input" name="RDATA[5]"  from="SB_RAM"/><port type="output" name="RDATA[5]" /></direct>
  <direct><port type="input" name="RDATA[6]"  from="SB_RAM"/><port type="output" name="RDATA[6]" /></direct>
  <direct><port type="input" name="RDATA[7]"  from="SB_RAM"/><port type="output" name="RDATA[7]" /></direct>
  <direct><port type="input" name="RDATA[8]"  from="SB_RAM"/><port type="output" name="RDATA[8]" /></direct>
  <direct><port type="input" name="RDATA[9]"  from="SB_RAM"/><port type="output" name="RDATA[9]" /></direct>
  <direct><port type="input" name="RDATA[10]" from="SB_RAM"/><port type="output" name="RDATA[10]"/></direct>
  <direct><port type="input" name="RDATA[11]" from="SB_RAM"/><port type="output" name="RDATA[11]"/></direct>
  <direct><port type="input" name="RDATA[12]" from="SB_RAM"/><port type="output" name="RDATA[12]"/></direct>
  <direct><port type="input" name="RDATA[13]" from="SB_RAM"/><port type="output" name="RDATA[13]"/></direct>
  <direct><port type="input" name="RDATA[14]" from="SB_RAM"/><port type="output" name="RDATA[14]"/></direct>
  <direct><port type="input" name="RDATA[15]" from="SB_RAM"/><port type="output" name="RDATA[15]"/></direct>

  <direct><port type="input" name="RADDR[0]" /><port type="output" name="RADDR[0]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[1]" /><port type="output" name="RADDR[1]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[2]" /><port type="output" name="RADDR[2]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[3]" /><port type="output" name="RADDR[3]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[4]" /><port type="output" name="RADDR[4]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[5]" /><port type="output" name="RADDR[5]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[6]" /><port type="output" name="RADDR[6]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[7]" /><port type="output" name="RADDR[7]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[8]" /><port type="output" name="RADDR[8]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[9]" /><port type="output" name="RADDR[9]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="RADDR[10]"/><port type="output" name="RADDR[10]" from="SB_RAM"/></direct>

  <direct><port type="input" name="RE"/><port type="output" name="RE" from="SB_RAM"/></direct>
  <direct><port type="input" name="RCLKE"/><port type="output" name="RCLKE" from="SB_RAM"/></direct>
  <direct><port type="input" name="RCLK"/><port type="output" name="RCLK" from="SB_RAM"/></direct>

  <direct><port type="input" name="WDATA[0]" /><port type="output" name="WDATA[0]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[1]" /><port type="output" name="WDATA[1]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[2]" /><port type="output" name="WDATA[2]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[3]" /><port type="output" name="WDATA[3]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[4]" /><port type="output" name="WDATA[4]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[5]" /><port type="output" name="WDATA[5]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[6]" /><port type="output" name="WDATA[6]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[7]" /><port type="output" name="WDATA[7]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[8]" /><port type="output" name="WDATA[8]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[9]" /><port type="output" name="WDATA[9]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[10]"/><port type="output" name="WDATA[10]" from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[11]"/><port type="output" name="WDATA[11]" from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[12]"/><port type="output" name="WDATA[12]" from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[13]"/><port type="output" name="WDATA[13]" from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[14]"/><port type="output" name="WDATA[14]" from="SB_RAM"/></direct>
  <direct><port type="input" name="WDATA[15]"/><port type="output" name="WDATA[15]" from="SB_RAM"/></direct>

  <direct><port type="input" name="MASK[0]" /><port type="output" name="MASK[0]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[1]" /><port type="output" name="MASK[1]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[2]" /><port type="output" name="MASK[2]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[3]" /><port type="output" name="MASK[3]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[4]" /><port type="output" name="MASK[4]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[5]" /><port type="output" name="MASK[5]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[6]" /><port type="output" name="MASK[6]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[7]" /><port type="output" name="MASK[7]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[8]" /><port type="output" name="MASK[8]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[9]" /><port type="output" name="MASK[9]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[10]"/><port type="output" name="MASK[10]" from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[11]"/><port type="output" name="MASK[11]" from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[12]"/><port type="output" name="MASK[12]" from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[13]"/><port type="output" name="MASK[13]" from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[14]"/><port type="output" name="MASK[14]" from="SB_RAM"/></direct>
  <direct><port type="input" name="MASK[15]"/><port type="output" name="MASK[15]" from="SB_RAM"/></direct>

  <direct><port type="input" name="WADDR[0]" /><port type="output" name="WADDR[0]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[1]" /><port type="output" name="WADDR[1]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[2]" /><port type="output" name="WADDR[2]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[3]" /><port type="output" name="WADDR[3]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[4]" /><port type="output" name="WADDR[4]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[5]" /><port type="output" name="WADDR[5]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[6]" /><port type="output" name="WADDR[6]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[7]" /><port type="output" name="WADDR[7]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[8]" /><port type="output" name="WADDR[8]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[9]" /><port type="output" name="WADDR[9]"  from="SB_RAM"/></direct>
  <direct><port type="input" name="WADDR[10]"/><port type="output" name="WADDR[10]" from="SB_RAM"/></direct>

  <direct><port type="input" name="WE"/><port type="output" name="WE" from="SB_RAM"/></direct>
  <direct><port type="input" name="WCLKE"/><port type="output" name="WCLKE" from="SB_RAM"/></direct>
  <direct><port type="input" name="WCLK"/><port type="output" name="WCLK" from="SB_RAM"/></direct>
 </interconnect>

 <fc in_type="abs" in_val="2" out_type="abs" out_val="2">
  <fc_override fc_type="abs" fc_val="2" port_name="RDATA" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RADDR" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RE"    segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RCLKE" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RCLK"  segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WDATA" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="MASK"  segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WADDR" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WE"    segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WCLKE" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WCLK"  segment_name="local"/>
 </fc>

 <pinlocations pattern="custom">
  <!-- RAM Tile -->
   <loc side="right" xoffset="0" yoffset="1">
   RAM.RDATA[8:15]
   RAM.MASK[8:15]
   RAM.WDATA[8:15]
   RAM.RADDR
   RAM.RCLKE
   RAM.RCLK
   RAM.RE
  </loc>
  <loc side="right" xoffset="0" yoffset="0">
   RAM.RDATA[0:7]
   RAM.MASK[0:7]
   RAM.WDATA[0:7]
   RAM.WADDR
   RAM.WCLKE
   RAM.WCLK
   RAM.WE
  </loc>
 </pinlocations>

 <switchblock_locations pattern="external_full_internal_straight"/>
 <metadata>
   <meta name="type">block</meta>
   <meta name="subtype">tile</meta>
 </metadata>
</pb_type>
<!-- End RAM -->

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