dff¶

Physical Block XML¶

<!-- set: ai sw=1 ts=1 sta et -->
<!-- Flip flop found inside the iCE40 -->
<pb_type name="DFF" num_pb="1">
 <clock  name="C" num_pins="1"/>
 <input  name="E" num_pins="1"/>
 <input  name="S" num_pins="1"/>
 <input  name="D" num_pins="1"/>
 <output name="Q" num_pins="1"/>

 <!-- Plain VPR flip flop -->
 <mode name="VPR_FF">
  <pb_type name="VPR_FF" num_pb="1" blif_model=".latch" class="flipflop">
   <clock  name="clk" num_pins="1" port_class="clock" />
   <input  name="D" num_pins="1" port_class="D" />
   <output name="Q" num_pins="1"  port_class="Q" />
   <T_setup    value="10e-12" port="D" clock="clk"/>
   <T_clock_to_Q max="10e-12" port="Q" clock="clk"/>
  </pb_type>
  <interconnect>
   <direct><port type="input" name="C"/><port type="output" from="VPR_FF" name="clk"/></direct>
   <direct><port type="input" name="D"/><port type="output" from="VPR_FF" name="D"/></direct>
   <direct><port type="input" from="VPR_FF" name="Q"/><port type="output" name="Q"/></direct>
  </interconnect>
 </mode>

 <!-- module SB_DFF (output Q, input C, D); -->
 <mode name="SB_DFF">
  <pb_type name="SB_DFF" num_pb="1" blif_model=".subckt SB_DFF">
   <output name="Q" num_pins="1"/>
   <clock  name="C" num_pins="1"/>
   <input  name="D" num_pins="1"/>
   <T_clock_to_Q max="10e-12" port="Q" clock="C"/>
   <T_setup    value="10e-12" port="D" clock="C"/>
  </pb_type>
  <interconnect>
   <direct><port type="input" from="SB_DFF" name="Q"/><port type="output" name="Q"/></direct>
   <direct><port type="input" name="C"/><port type="output" from="SB_DFF" name="C"/></direct>
   <direct><port type="input" name="D"/><port type="output" from="SB_DFF" name="D"/></direct>
  </interconnect>
 </mode>
</pb_type>