symbiflow-arch-defs
symbiflow-arch-defs

ramb

Physical Block XML

<!-- set: ai sw=1 ts=1 sta et -->
<!-- A diagram for the iCE40 PLB "Block RAM" is shown in;
      http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf
  -->
<pb_type name="RAMB" height="1" xmlns:xi="http://www.w3.org/2001/XInclude">
 <!-- Read port -->
 <output name="RDATAT" num_pins="8"/>
 <output name="RDATAB" num_pins="8"/>
 <input  name="RADDR"  num_pins="11"/>
 <input  name="RE"     num_pins="1"/>
 <input  name="RCLKE"  num_pins="1"/>
 <clock  name="RCLK"   num_pins="1"/>
 <!-- Write port -->
 <input  name="WDATAT" num_pins="8"/>
 <input  name="WDATAB" num_pins="8"/>
 <input  name="MASKT"  num_pins="8"/>
 <input  name="MASKB"  num_pins="8"/>
 <input  name="WADDR"  num_pins="11"/>
 <input  name="WE"     num_pins="1"/>
 <input  name="WCLKE"  num_pins="1"/>
 <clock  name="WCLK"   num_pins="1"/>

 <xi:include href="../../../../primitives/sb_ram/sb_ram.pb_type.xml"/>

 <interconnect>
  <direct name="RDATA00" input="SB_RAM.RDATA[0]"  output="RAMB.RDATAT[0]"/>
  <direct name="RDATA01" input="SB_RAM.RDATA[1]"  output="RAMB.RDATAT[1]"/>
  <direct name="RDATA02" input="SB_RAM.RDATA[2]"  output="RAMB.RDATAT[2]"/>
  <direct name="RDATA03" input="SB_RAM.RDATA[3]"  output="RAMB.RDATAT[3]"/>
  <direct name="RDATA04" input="SB_RAM.RDATA[4]"  output="RAMB.RDATAT[4]"/>
  <direct name="RDATA05" input="SB_RAM.RDATA[5]"  output="RAMB.RDATAT[5]"/>
  <direct name="RDATA06" input="SB_RAM.RDATA[6]"  output="RAMB.RDATAT[6]"/>
  <direct name="RDATA07" input="SB_RAM.RDATA[7]"  output="RAMB.RDATAT[7]"/>

  <direct name="RDATA08" input="SB_RAM.RDATA[8]"  output="RAMB.RDATAB[0]"/>
  <direct name="RDATA09" input="SB_RAM.RDATA[9]"  output="RAMB.RDATAB[1]"/>
  <direct name="RDATA10" input="SB_RAM.RDATA[10]" output="RAMB.RDATAB[2]"/>
  <direct name="RDATA11" input="SB_RAM.RDATA[11]" output="RAMB.RDATAB[3]"/>
  <direct name="RDATA12" input="SB_RAM.RDATA[12]" output="RAMB.RDATAB[4]"/>
  <direct name="RDATA13" input="SB_RAM.RDATA[13]" output="RAMB.RDATAB[5]"/>
  <direct name="RDATA14" input="SB_RAM.RDATA[14]" output="RAMB.RDATAB[6]"/>
  <direct name="RDATA15" input="SB_RAM.RDATA[15]" output="RAMB.RDATAB[7]"/>

  <direct name="RADDR00" input="RAMB.RADDR[0]"  output="SB_RAM.RADDR[0]"/>
  <direct name="RADDR01" input="RAMB.RADDR[1]"  output="SB_RAM.RADDR[1]"/>
  <direct name="RADDR02" input="RAMB.RADDR[2]"  output="SB_RAM.RADDR[2]"/>
  <direct name="RADDR03" input="RAMB.RADDR[3]"  output="SB_RAM.RADDR[3]"/>
  <direct name="RADDR04" input="RAMB.RADDR[4]"  output="SB_RAM.RADDR[4]"/>
  <direct name="RADDR05" input="RAMB.RADDR[5]"  output="SB_RAM.RADDR[5]"/>
  <direct name="RADDR06" input="RAMB.RADDR[6]"  output="SB_RAM.RADDR[6]"/>
  <direct name="RADDR07" input="RAMB.RADDR[7]"  output="SB_RAM.RADDR[7]"/>
  <direct name="RADDR08" input="RAMB.RADDR[8]"  output="SB_RAM.RADDR[8]"/>
  <direct name="RADDR09" input="RAMB.RADDR[9]"  output="SB_RAM.RADDR[9]"/>
  <direct name="RADDR10" input="RAMB.RADDR[10]" output="SB_RAM.RADDR[10]"/>

  <direct name="RE"      input="RAMB.RE"        output="SB_RAM.RE" />
  <direct name="RCLKE"   input="RAMB.RCLKE"     output="SB_RAM.RCLKE" />
  <direct name="RCLK"    input="RAMB.RCLK"      output="SB_RAM.RCLK" />

  <direct name="WDATA00" input="RAMB.WDATAT[0]" output="SB_RAM.WDATA[0]"/>
  <direct name="WDATA01" input="RAMB.WDATAT[1]" output="SB_RAM.WDATA[1]"/>
  <direct name="WDATA02" input="RAMB.WDATAT[2]" output="SB_RAM.WDATA[2]"/>
  <direct name="WDATA03" input="RAMB.WDATAT[3]" output="SB_RAM.WDATA[3]"/>
  <direct name="WDATA04" input="RAMB.WDATAT[4]" output="SB_RAM.WDATA[4]"/>
  <direct name="WDATA05" input="RAMB.WDATAT[5]" output="SB_RAM.WDATA[5]"/>
  <direct name="WDATA06" input="RAMB.WDATAT[6]" output="SB_RAM.WDATA[6]"/>
  <direct name="WDATA07" input="RAMB.WDATAT[7]" output="SB_RAM.WDATA[7]"/>

  <direct name="WDATA08" input="RAMB.WDATAB[0]" output="SB_RAM.WDATA[8]"/>
  <direct name="WDATA09" input="RAMB.WDATAB[1]" output="SB_RAM.WDATA[9]"/>
  <direct name="WDATA10" input="RAMB.WDATAB[2]" output="SB_RAM.WDATA[10]"/>
  <direct name="WDATA11" input="RAMB.WDATAB[3]" output="SB_RAM.WDATA[11]"/>
  <direct name="WDATA12" input="RAMB.WDATAB[4]" output="SB_RAM.WDATA[12]"/>
  <direct name="WDATA13" input="RAMB.WDATAB[5]" output="SB_RAM.WDATA[13]"/>
  <direct name="WDATA14" input="RAMB.WDATAB[6]" output="SB_RAM.WDATA[14]"/>
  <direct name="WDATA15" input="RAMB.WDATAB[7]" output="SB_RAM.WDATA[15]"/>

  <direct name="MASK00" input="RAMB.MASKT[0]" output="SB_RAM.MASK[0]"/>
  <direct name="MASK01" input="RAMB.MASKT[1]" output="SB_RAM.MASK[1]"/>
  <direct name="MASK02" input="RAMB.MASKT[2]" output="SB_RAM.MASK[2]"/>
  <direct name="MASK03" input="RAMB.MASKT[3]" output="SB_RAM.MASK[3]"/>
  <direct name="MASK04" input="RAMB.MASKT[4]" output="SB_RAM.MASK[4]"/>
  <direct name="MASK05" input="RAMB.MASKT[5]" output="SB_RAM.MASK[5]"/>
  <direct name="MASK06" input="RAMB.MASKT[6]" output="SB_RAM.MASK[6]"/>
  <direct name="MASK07" input="RAMB.MASKT[7]" output="SB_RAM.MASK[7]"/>

  <direct name="MASK08" input="RAMB.MASKB[0]" output="SB_RAM.MASK[8]"/>
  <direct name="MASK09" input="RAMB.MASKB[1]" output="SB_RAM.MASK[9]"/>
  <direct name="MASK10" input="RAMB.MASKB[2]" output="SB_RAM.MASK[10]"/>
  <direct name="MASK11" input="RAMB.MASKB[3]" output="SB_RAM.MASK[11]"/>
  <direct name="MASK12" input="RAMB.MASKB[4]" output="SB_RAM.MASK[12]"/>
  <direct name="MASK13" input="RAMB.MASKB[5]" output="SB_RAM.MASK[13]"/>
  <direct name="MASK14" input="RAMB.MASKB[6]" output="SB_RAM.MASK[14]"/>
  <direct name="MASK15" input="RAMB.MASKB[7]" output="SB_RAM.MASK[15]"/>

  <direct name="WADDR00" input="RAMB.WADDR[0]"  output="SB_RAM.WADDR[0]"/>
  <direct name="WADDR01" input="RAMB.WADDR[1]"  output="SB_RAM.WADDR[1]"/>
  <direct name="WADDR02" input="RAMB.WADDR[2]"  output="SB_RAM.WADDR[2]"/>
  <direct name="WADDR03" input="RAMB.WADDR[3]"  output="SB_RAM.WADDR[3]"/>
  <direct name="WADDR04" input="RAMB.WADDR[4]"  output="SB_RAM.WADDR[4]"/>
  <direct name="WADDR05" input="RAMB.WADDR[5]"  output="SB_RAM.WADDR[5]"/>
  <direct name="WADDR06" input="RAMB.WADDR[6]"  output="SB_RAM.WADDR[6]"/>
  <direct name="WADDR07" input="RAMB.WADDR[7]"  output="SB_RAM.WADDR[7]"/>
  <direct name="WADDR08" input="RAMB.WADDR[8]"  output="SB_RAM.WADDR[8]"/>
  <direct name="WADDR09" input="RAMB.WADDR[9]"  output="SB_RAM.WADDR[9]"/>
  <direct name="WADDR10" input="RAMB.WADDR[10]" output="SB_RAM.WADDR[10]"/>

  <direct name="WE"    input="RAMB.WE"          output="SB_RAM.WE" />
  <direct name="WCLKE" input="RAMB.WCLKE"       output="SB_RAM.WCLKE" />
  <direct name="WCLK"  input="RAMB.WCLK"        output="SB_RAM.WCLK" />
 </interconnect>

 <fc in_type="abs" in_val="2" out_type="abs" out_val="2">
  <fc_override fc_type="abs" fc_val="2" port_name="RDATAT" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RDATAB" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RADDR"  segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RE"     segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RCLKE"  segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="RCLK"   segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WDATAT" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WDATAB" segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="MASKT"  segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="MASKB"  segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WADDR"  segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WE"     segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WCLKE"  segment_name="local"/>
  <fc_override fc_type="abs" fc_val="2" port_name="WCLK"   segment_name="local"/>
 </fc>

 <pinlocations pattern="custom">
  <!-- RAMB Tile -->
  <loc side="right" xoffset="0" yoffset="0">
   RAMB.RDATAB
   RAMB.WADDR
   RAMB.MASKB
   RAMB.WDATAB
   RAMB.WCLKE
   RAMB.WCLK
   RAMB.WE
   RAMB.RDATAT
   RAMB.RADDR
   RAMB.MASKT
   RAMB.WDATAT
   RAMB.RCLKE
   RAMB.RCLK
   RAMB.RE
  </loc>
 </pinlocations>
 <!--
  </loc>
  <loc side="right" xoffset="0" yoffset="1"> -->
 <switchblock_locations pattern="external_full_internal_straight"/>
 <metadata>
  <meta name="type">block</meta>
  <meta name="subtype">tile</meta>
 </metadata>
</pb_type>
<!-- End RAMB -->

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