tieoff
===============================================================================



Component Diagram
-----------------

.. symbolator:: ../../../../../xc/common/primitives/tieoff/tieoff.sim.v

   

Internal Diagram
----------------

.. verilog-diagram:: ../../../../../xc/common/primitives/tieoff/tieoff.sim.v
   :type: netlistsvg
   :module: TIEOFF

   

Verilog File
------------

.. literalinclude:: ../../../../../xc/common/primitives/tieoff/tieoff.sim.v
   :language: verilog