plle2_adv¶
Physical Block XML¶
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="PLLE2_ADV" blif_model=".subckt PLLE2_ADV_VPR" num_pb="1">
<clock name="DCLK" num_pins="1"/>
<input name="DEN" num_pins="1"/>
<input name="DWE" num_pins="1"/>
<input name="DADDR" num_pins="7"/>
<input name="DI" num_pins="16"/>
<clock name="CLKFBIN" num_pins="1"/>
<clock name="CLKIN1" num_pins="1"/>
<clock name="CLKIN2" num_pins="1"/>
<input name="CLKINSEL" num_pins="1"/>
<input name="PWRDWN" num_pins="1"/>
<input name="RST" num_pins="1"/>
<output name="DO" num_pins="16"/>
<output name="DRDY" num_pins="1"/>
<output name="CLKFBOUT" num_pins="1"/>
<output name="CLKOUT0" num_pins="1"/>
<output name="CLKOUT1" num_pins="1"/>
<output name="CLKOUT2" num_pins="1"/>
<output name="CLKOUT3" num_pins="1"/>
<output name="CLKOUT4" num_pins="1"/>
<output name="CLKOUT5" num_pins="1"/>
<output name="LOCKED" num_pins="1"/>
<T_setup value="{setup_DCLK_DEN}" port="DEN" clock="DCLK"/>
<T_hold value="{hold_DCLK_DEN}" port="DEN" clock="DCLK"/>
<T_setup value="{setup_DCLK_DWE}" port="DWE" clock="DCLK"/>
<T_hold value="{hold_DCLK_DWE}" port="DWE" clock="DCLK"/>
<T_setup value="{setup_DCLK_DADDR}" port="DADDR" clock="DCLK"/>
<T_hold value="{hold_DCLK_DADDR}" port="DADDR" clock="DCLK"/>
<T_setup value="{setup_DCLK_DI}" port="DI" clock="DCLK"/>
<T_hold value="{hold_DCLK_DI}" port="DI" clock="DCLK"/>
<T_clock_to_Q max="{iopath_DCLK_DO}" port="DO" clock="DCLK"/>
<T_clock_to_Q max="{iopath_DCLK_DRDY}" port="DRDY" clock="DCLK"/>
<delay_constant max="{iopath_RST_LOCKED}" in_port="RST" out_port="LOCKED"/>
<!-- The following timings depend on the PLL COMPENSATION setting.
For now the worst ones were chosen (for the "BUF_IN" mode). This may
be changed in the bels.json file -->
<!-- FIXME: delay constants are not allowed for clock generators as the combinational sink
cannot be used in the model
<delay_constant max="{iopath_CLKIN1_CLKFBOUT}" in_port="CLKIN1" out_port="CLKFBOUT"/>
<delay_constant max="{iopath_CLKIN1_CLKOUT0}" in_port="CLKIN1" out_port="CLKOUT0"/>
<delay_constant max="{iopath_CLKIN1_CLKOUT1}" in_port="CLKIN1" out_port="CLKOUT1"/>
<delay_constant max="{iopath_CLKIN1_CLKOUT2}" in_port="CLKIN1" out_port="CLKOUT2"/>
<delay_constant max="{iopath_CLKIN1_CLKOUT3}" in_port="CLKIN1" out_port="CLKOUT3"/>
<delay_constant max="{iopath_CLKIN1_CLKOUT4}" in_port="CLKIN1" out_port="CLKOUT4"/>
<delay_constant max="{iopath_CLKIN1_CLKOUT5}" in_port="CLKIN1" out_port="CLKOUT5"/>
<delay_constant max="{iopath_CLKIN2_CLKFBOUT}" in_port="CLKIN2" out_port="CLKFBOUT"/>
<delay_constant max="{iopath_CLKIN2_CLKOUT0}" in_port="CLKIN2" out_port="CLKOUT0"/>
<delay_constant max="{iopath_CLKIN2_CLKOUT1}" in_port="CLKIN2" out_port="CLKOUT1"/>
<delay_constant max="{iopath_CLKIN2_CLKOUT2}" in_port="CLKIN2" out_port="CLKOUT2"/>
<delay_constant max="{iopath_CLKIN2_CLKOUT3}" in_port="CLKIN2" out_port="CLKOUT3"/>
<delay_constant max="{iopath_CLKIN2_CLKOUT4}" in_port="CLKIN2" out_port="CLKOUT4"/>
<delay_constant max="{iopath_CLKIN2_CLKOUT5}" in_port="CLKIN2" out_port="CLKOUT5"/> -->
<!-- Metadata -->
<metadata>
<meta name="fasm_prefix">
PLLE2
</meta>
<meta name="fasm_features">
IN_USE
COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF
</meta>
<meta name="fasm_params">
INV_CLKINSEL = INV_CLKINSEL
ZINV_PWRDWN = ZINV_PWRDWN
ZINV_RST = ZINV_RST
STARTUP_WAIT = STARTUP_WAIT
DIVCLK_DIVCLK_HIGH_TIME[5:0] = DIVCLK_DIVCLK_HIGH_TIME
DIVCLK_DIVCLK_LOW_TIME[5:0] = DIVCLK_DIVCLK_LOW_TIME
DIVCLK_DIVCLK_NO_COUNT = DIVCLK_DIVCLK_NO_COUNT
DIVCLK_DIVCLK_EDGE = DIVCLK_DIVCLK_EDGE
TABLE[9:0] = TABLE
LKTABLE[39:0] = LKTABLE
POWER_REG_POWER_REG_POWER_REG[15:0] = POWER_REG
FILTREG1_RESERVED[11:0] = FILTREG1_RESERVED
FILTREG2_RESERVED[9:0] = FILTREG2_RESERVED
LOCKREG1_RESERVED[5:0] = LOCKREG1_RESERVED
LOCKREG2_RESERVED = LOCKREG2_RESERVED
LOCKREG3_RESERVED = LOCKREG3_RESERVED
CLKFBOUT_CLKOUT1_HIGH_TIME[5:0] = CLKFBOUT_CLKOUT1_HIGH_TIME
CLKFBOUT_CLKOUT1_LOW_TIME[5:0] = CLKFBOUT_CLKOUT1_LOW_TIME
CLKFBOUT_CLKOUT1_OUTPUT_ENABLE = CLKFBOUT_CLKOUT1_OUTPUT_ENABLE
CLKFBOUT_CLKOUT1_PHASE_MUX[2:0] = CLKFBOUT_CLKOUT1_PHASE_MUX
CLKFBOUT_CLKOUT2_DELAY_TIME[5:0] = CLKFBOUT_CLKOUT2_DELAY_TIME
CLKFBOUT_CLKOUT2_EDGE = CLKFBOUT_CLKOUT2_EDGE
CLKFBOUT_CLKOUT2_FRAC[2:0] = CLKFBOUT_CLKOUT2_FRAC
CLKFBOUT_CLKOUT2_FRAC_EN = CLKFBOUT_CLKOUT2_FRAC_EN
CLKFBOUT_CLKOUT2_FRAC_WF_R = CLKFBOUT_CLKOUT2_FRAC_WF_R
CLKFBOUT_CLKOUT2_NO_COUNT = CLKFBOUT_CLKOUT2_NO_COUNT
CLKOUT0_CLKOUT1_HIGH_TIME[5:0] = CLKOUT0_CLKOUT1_HIGH_TIME
CLKOUT0_CLKOUT1_LOW_TIME[5:0] = CLKOUT0_CLKOUT1_LOW_TIME
CLKOUT0_CLKOUT1_OUTPUT_ENABLE = CLKOUT0_CLKOUT1_OUTPUT_ENABLE
CLKOUT0_CLKOUT1_PHASE_MUX[2:0] = CLKOUT0_CLKOUT1_PHASE_MUX
CLKOUT0_CLKOUT2_DELAY_TIME[5:0] = CLKOUT0_CLKOUT2_DELAY_TIME
CLKOUT0_CLKOUT2_EDGE = CLKOUT0_CLKOUT2_EDGE
CLKOUT0_CLKOUT2_FRAC[2:0] = CLKOUT0_CLKOUT2_FRAC
CLKOUT0_CLKOUT2_FRAC_EN = CLKOUT0_CLKOUT2_FRAC_EN
CLKOUT0_CLKOUT2_FRAC_WF_R = CLKOUT0_CLKOUT2_FRAC_WF_R
CLKOUT0_CLKOUT2_NO_COUNT = CLKOUT0_CLKOUT2_NO_COUNT
CLKOUT1_CLKOUT1_HIGH_TIME[5:0] = CLKOUT1_CLKOUT1_HIGH_TIME
CLKOUT1_CLKOUT1_LOW_TIME[5:0] = CLKOUT1_CLKOUT1_LOW_TIME
CLKOUT1_CLKOUT1_OUTPUT_ENABLE = CLKOUT1_CLKOUT1_OUTPUT_ENABLE
CLKOUT1_CLKOUT1_PHASE_MUX[2:0] = CLKOUT1_CLKOUT1_PHASE_MUX
CLKOUT1_CLKOUT2_DELAY_TIME[5:0] = CLKOUT1_CLKOUT2_DELAY_TIME
CLKOUT1_CLKOUT2_EDGE = CLKOUT1_CLKOUT2_EDGE
CLKOUT1_CLKOUT2_FRAC[2:0] = CLKOUT1_CLKOUT2_FRAC
CLKOUT1_CLKOUT2_FRAC_EN = CLKOUT1_CLKOUT2_FRAC_EN
CLKOUT1_CLKOUT2_FRAC_WF_R = CLKOUT1_CLKOUT2_FRAC_WF_R
CLKOUT1_CLKOUT2_NO_COUNT = CLKOUT1_CLKOUT2_NO_COUNT
CLKOUT2_CLKOUT1_HIGH_TIME[5:0] = CLKOUT2_CLKOUT1_HIGH_TIME
CLKOUT2_CLKOUT1_LOW_TIME[5:0] = CLKOUT2_CLKOUT1_LOW_TIME
CLKOUT2_CLKOUT1_OUTPUT_ENABLE = CLKOUT2_CLKOUT1_OUTPUT_ENABLE
CLKOUT2_CLKOUT1_PHASE_MUX[2:0] = CLKOUT2_CLKOUT1_PHASE_MUX
CLKOUT2_CLKOUT2_DELAY_TIME[5:0] = CLKOUT2_CLKOUT2_DELAY_TIME
CLKOUT2_CLKOUT2_EDGE = CLKOUT2_CLKOUT2_EDGE
CLKOUT2_CLKOUT2_FRAC[2:0] = CLKOUT2_CLKOUT2_FRAC
CLKOUT2_CLKOUT2_FRAC_EN = CLKOUT2_CLKOUT2_FRAC_EN
CLKOUT2_CLKOUT2_FRAC_WF_R = CLKOUT2_CLKOUT2_FRAC_WF_R
CLKOUT2_CLKOUT2_NO_COUNT = CLKOUT2_CLKOUT2_NO_COUNT
CLKOUT3_CLKOUT1_HIGH_TIME[5:0] = CLKOUT3_CLKOUT1_HIGH_TIME
CLKOUT3_CLKOUT1_LOW_TIME[5:0] = CLKOUT3_CLKOUT1_LOW_TIME
CLKOUT3_CLKOUT1_OUTPUT_ENABLE = CLKOUT3_CLKOUT1_OUTPUT_ENABLE
CLKOUT3_CLKOUT1_PHASE_MUX[2:0] = CLKOUT3_CLKOUT1_PHASE_MUX
CLKOUT3_CLKOUT2_DELAY_TIME[5:0] = CLKOUT3_CLKOUT2_DELAY_TIME
CLKOUT3_CLKOUT2_EDGE = CLKOUT3_CLKOUT2_EDGE
CLKOUT3_CLKOUT2_FRAC[2:0] = CLKOUT3_CLKOUT2_FRAC
CLKOUT3_CLKOUT2_FRAC_EN = CLKOUT3_CLKOUT2_FRAC_EN
CLKOUT3_CLKOUT2_FRAC_WF_R = CLKOUT3_CLKOUT2_FRAC_WF_R
CLKOUT3_CLKOUT2_NO_COUNT = CLKOUT3_CLKOUT2_NO_COUNT
CLKOUT4_CLKOUT1_HIGH_TIME[5:0] = CLKOUT4_CLKOUT1_HIGH_TIME
CLKOUT4_CLKOUT1_LOW_TIME[5:0] = CLKOUT4_CLKOUT1_LOW_TIME
CLKOUT4_CLKOUT1_OUTPUT_ENABLE = CLKOUT4_CLKOUT1_OUTPUT_ENABLE
CLKOUT4_CLKOUT1_PHASE_MUX[2:0] = CLKOUT4_CLKOUT1_PHASE_MUX
CLKOUT4_CLKOUT2_DELAY_TIME[5:0] = CLKOUT4_CLKOUT2_DELAY_TIME
CLKOUT4_CLKOUT2_EDGE = CLKOUT4_CLKOUT2_EDGE
CLKOUT4_CLKOUT2_FRAC[2:0] = CLKOUT4_CLKOUT2_FRAC
CLKOUT4_CLKOUT2_FRAC_EN = CLKOUT4_CLKOUT2_FRAC_EN
CLKOUT4_CLKOUT2_FRAC_WF_R = CLKOUT4_CLKOUT2_FRAC_WF_R
CLKOUT4_CLKOUT2_NO_COUNT = CLKOUT4_CLKOUT2_NO_COUNT
CLKOUT5_CLKOUT1_HIGH_TIME[5:0] = CLKOUT5_CLKOUT1_HIGH_TIME
CLKOUT5_CLKOUT1_LOW_TIME[5:0] = CLKOUT5_CLKOUT1_LOW_TIME
CLKOUT5_CLKOUT1_OUTPUT_ENABLE = CLKOUT5_CLKOUT1_OUTPUT_ENABLE
CLKOUT5_CLKOUT1_PHASE_MUX[2:0] = CLKOUT5_CLKOUT1_PHASE_MUX
CLKOUT5_CLKOUT2_DELAY_TIME[5:0] = CLKOUT5_CLKOUT2_DELAY_TIME
CLKOUT5_CLKOUT2_EDGE = CLKOUT5_CLKOUT2_EDGE
CLKOUT5_CLKOUT2_FRAC[2:0] = CLKOUT5_CLKOUT2_FRAC
CLKOUT5_CLKOUT2_FRAC_EN = CLKOUT5_CLKOUT2_FRAC_EN
CLKOUT5_CLKOUT2_FRAC_WF_R = CLKOUT5_CLKOUT2_FRAC_WF_R
CLKOUT5_CLKOUT2_NO_COUNT = CLKOUT5_CLKOUT2_NO_COUNT
</meta>
</metadata>
</pb_type>
Model XML¶
<models>
<model name="PLLE2_ADV_VPR">
<input_ports>
<port is_clock="1" name="DCLK"/>
<port clock="DCLK" name="DEN"/>
<port clock="DCLK" name="DWE"/>
<port clock="DCLK" name="DADDR"/>
<port clock="DCLK" name="DI"/>
<port is_clock="1" name="CLKFBIN"/>
<port is_clock="1" name="CLKIN1"/>
<port is_clock="1" name="CLKIN2"/>
<port name="CLKINSEL"/>
<port name="PWRDWN"/>
<port name="RST" combinational_sink_ports="LOCKED"/>
</input_ports>
<output_ports>
<port clock="DCLK" name="DO"/>
<port clock="DCLK" name="DRDY"/>
<port is_clock="1" name="CLKFBOUT"/>
<port is_clock="1" name="CLKOUT0"/>
<port is_clock="1" name="CLKOUT1"/>
<port is_clock="1" name="CLKOUT2"/>
<port is_clock="1" name="CLKOUT3"/>
<port is_clock="1" name="CLKOUT4"/>
<port is_clock="1" name="CLKOUT5"/>
<port name="LOCKED"/>
</output_ports>
</model>
</models>