clkinv¶
Component Diagram¶
Internal Diagram¶
Verilog File¶
`include "../../../../../../vpr/muxes/logic/mux2/mux2.sim.v"
module CLKINV(CLK, OUT);
input wire CLK;
parameter INV = 0;
output wire OUT;
MUX2 mux (
.I0(CLK),
.I1(~CLK),
.S0(INV),
.O(OUT)
);
endmodule
Physical Block XML¶
<pb_type name="CLKINV" num_pb="1">
<input name="CLK" num_pins="1"/>
<output name="OUT" num_pins="1"/>
<interconnect>
<mux input="CLKINV.CLK" name="_CLKINV" output="CLKINV.OUT"/>
</interconnect>
</pb_type>