bufgctrl¶

Physical Block XML¶

<!-- Model of BUFG group in BUFG_CLK_TOP/BOT -->
<pb_type name="BLK-TL-BUFGCTRL" xmlns:xi="http://www.w3.org/2001/XInclude">
  <output name="O" num_pins="1"/>
  <input name="CE0" num_pins="1"/>
  <input name="CE1" num_pins="1"/>
  <clock name="I0" num_pins="1"/>
  <clock name="I1" num_pins="1"/>
  <input name="IGNORE0" num_pins="1"/>
  <input name="IGNORE1" num_pins="1"/>
  <input name="S0" num_pins="1"/>
  <input name="S1" num_pins="1"/>
  <mode name="EMPTY">
    <pb_type name="empty" blif_model=".latch" num_pb="1" />
    <interconnect />
  </mode>
  <mode name="BUFGCTRL">
    <pb_type name="BUFGCTRL_VPR" blif_model=".subckt BUFGCTRL_VPR" num_pb="1">
      <output name="O" num_pins="1"/>
      <input name="CE0" num_pins="1"/>
      <input name="CE1" num_pins="1"/>
      <clock name="I0" num_pins="1"/>
      <clock name="I1" num_pins="1"/>
      <input name="IGNORE0" num_pins="1"/>
      <input name="IGNORE1" num_pins="1"/>
      <input name="S0" num_pins="1"/>
      <input name="S1" num_pins="1"/>
      <!-- FIXME: delay constants cannot be used as there is no
           combinational sink from I0/I1 to the O pin
      <delay_constant max="{iopath_I_O}" in_port="I0" out_port="O"/>
      <delay_constant max="{iopath_I_O}" in_port="I1" out_port="O"/>
      -->
      <metadata>
        <meta name="fasm_params">
          ZPRESELECT_I0 = ZPRESELECT_I0
          ZPRESELECT_I1 = ZPRESELECT_I1
          IS_IGNORE0_INVERTED = IS_IGNORE0_INVERTED
          IS_IGNORE1_INVERTED = IS_IGNORE1_INVERTED
          ZINV_CE0 = ZINV_CE0
          ZINV_CE1 = ZINV_CE1
          ZINV_S0 = ZINV_S0
          ZINV_S1 = ZINV_S1
        </meta>
      </metadata>
    </pb_type>
    <interconnect>
      <direct name="O" input="BUFGCTRL_VPR.O" output="BLK-TL-BUFGCTRL.O"/>
      <direct name="CE0" input="BLK-TL-BUFGCTRL.CE0" output="BUFGCTRL_VPR.CE0"/>
      <direct name="CE1" input="BLK-TL-BUFGCTRL.CE1" output="BUFGCTRL_VPR.CE1"/>
      <direct name="I0" input="BLK-TL-BUFGCTRL.I0" output="BUFGCTRL_VPR.I0"/>
      <direct name="I1" input="BLK-TL-BUFGCTRL.I1" output="BUFGCTRL_VPR.I1"/>
      <direct name="IGNORE0" input="BLK-TL-BUFGCTRL.IGNORE0" output="BUFGCTRL_VPR.IGNORE0"/>
      <direct name="IGNORE1" input="BLK-TL-BUFGCTRL.IGNORE1" output="BUFGCTRL_VPR.IGNORE1"/>
      <direct name="S0" input="BLK-TL-BUFGCTRL.S0" output="BUFGCTRL_VPR.S0"/>
      <direct name="S1" input="BLK-TL-BUFGCTRL.S1" output="BUFGCTRL_VPR.S1"/>

    </interconnect>
    <metadata>
      <meta name="fasm_features">
        IN_USE
      </meta>
    </metadata>
  </mode>
</pb_type>

Model XML¶

<!-- vim: set ai sw=1 ts=1 sta et: -->
<models xmlns:xi="http://www.w3.org/2001/XInclude">
 <model name="BUFGCTRL_VPR">
  <input_ports>
   <port name="CE0" />
   <port name="CE1" />
   <port name="I0" is_clock="1"/>
   <port name="I1" is_clock="1"/>
   <port name="IGNORE0" />
   <port name="IGNORE1" />
   <port name="S0" />
   <port name="S1" />
  </input_ports>
  <output_ports>
   <port name="O" is_clock="1"/>
  </output_ports>
 </model>
</models>