a_srl¶

Physical Block XML¶

<!-- The ASRL is special in a way that it is last in the SRL chain in the slice.
     therefore some pack patterns need to be different than for the other 3.
     Hence the ASRL is not a part of the N template -->

<pb_type name="ASRL" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
  <clock  name="CLK" num_pins="1"/>
  <input  name="WE" num_pins="1"/>
  <input  name="A1" num_pins="1"/>
  <input  name="A2" num_pins="1"/>
  <input  name="A3" num_pins="1"/>
  <input  name="A4" num_pins="1"/>
  <input  name="A5" num_pins="1"/>
  <input  name="A6" num_pins="1"/>
  <input  name="DI1_SRL16" num_pins="1"/>
  <input  name="DI1_SRL32" num_pins="1"/>
  <input  name="DI2" num_pins="1"/>
  <output name="O5" num_pins="1"/>
  <output name="O6" num_pins="1"/>
  <output name="MC31" num_pins="1"/>

  <mode name="SRL32">
    <xi:include href="srlc32e_vpr.pb_type.xml" />
    <interconnect>
      <direct name="CLK" input="ASRL.CLK" output="SRLC32E_VPR.CLK"/>
      <direct name="WE" input="ASRL.WE" output="SRLC32E_VPR.CE"/>
      <direct name="DI1" input="ASRL.DI1_SRL32" output="SRLC32E_VPR.D"/>
      <direct name="A2" input="ASRL.A2" output="SRLC32E_VPR.A[0]"/>
      <direct name="A3" input="ASRL.A3" output="SRLC32E_VPR.A[1]"/>
      <direct name="A4" input="ASRL.A4" output="SRLC32E_VPR.A[2]"/>
      <direct name="A5" input="ASRL.A5" output="SRLC32E_VPR.A[3]"/>
      <direct name="A6" input="ASRL.A6" output="SRLC32E_VPR.A[4]"/>
      <direct name="O6" input="SRLC32E_VPR.Q" output="ASRL.O6"/>
      <direct name="MC31" input="SRLC32E_VPR.Q31" output="ASRL.MC31"/>
    </interconnect>
  </mode>

  <mode name="2xSRL16">
    <xi:include href="srlc16e_vpr_0.pb_type.xml"/>
    <xi:include href="srlc16e_vpr_1.pb_type.xml"/>
    <interconnect>
      <direct name="CLK_0" input="ASRL.CLK" output="SRLC16E_VPR_0.CLK"/>
      <direct name="WE_0" input="ASRL.WE" output="SRLC16E_VPR_0.CE"/>
      <direct name="DI1" input="ASRL.DI1_SRL16" output="SRLC16E_VPR_0.D"/>
      <direct name="A2_0" input="ASRL.A2" output="SRLC16E_VPR_0.A0"/>
      <direct name="A3_0" input="ASRL.A3" output="SRLC16E_VPR_0.A1"/>
      <direct name="A4_0" input="ASRL.A4" output="SRLC16E_VPR_0.A2"/>
      <direct name="A5_0" input="ASRL.A5" output="SRLC16E_VPR_0.A3"/>
      <direct name="O5" input="SRLC16E_VPR_0.Q" output="ASRL.O5"/>

      <direct name="CLK_1" input="ASRL.CLK" output="SRLC16E_VPR_1.CLK"/>
      <direct name="WE_1" input="ASRL.WE" output="SRLC16E_VPR_1.CE"/>
      <direct name="DI2" input="ASRL.DI2" output="SRLC16E_VPR_1.D"/>
      <direct name="A2_1" input="ASRL.A2" output="SRLC16E_VPR_1.A0"/>
      <direct name="A3_1" input="ASRL.A3" output="SRLC16E_VPR_1.A1"/>
      <direct name="A4_1" input="ASRL.A4" output="SRLC16E_VPR_1.A2"/>
      <direct name="A5_1" input="ASRL.A5" output="SRLC16E_VPR_1.A3"/>
      <direct name="O6" input="SRLC16E_VPR_1.Q" output="ASRL.O6"/>
      <direct name="MC31" input="SRLC16E_VPR_1.Q15" output="ASRL.MC31"/>
    </interconnect>
  </mode>

  <metadata>
    <meta name="fasm_prefix">
      ALUT
    </meta>
  </metadata>
</pb_type>