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symbiflow-arch-defs
Table Of Contents
Getting Started
Development Practices
Structure
Verilog To Routing Notes
Project X-Ray
Flow Diagram
VPR routing graph
Xilinx 7 Series SymbiFlow Partial Reconfiguration Flow
Index of Primitive Models
a_srl
alu
b_dram
bram
bram_l
bram_r
bufgctrl
carry0
carry4_vpr
carryinsel_logic
ceusedmux
clkinv
common_lut_and_f78mux
common_slice
coutused
d_dram
d_dram128
di64_stub
dpram32
dpram64
dpram64_for_ram128x1d
dram_2_output_stub
dram_4_output_stub
dram_8_output_stub
dsp48e1
dual_ad_preadder
dual_b_reg
ff
idelayctrl
idelaye2
ilogice3
inpad
iob33
iob33m
iob33s
mult25x18
nmux2
nreg
ologice3
outpad
plle2_adv
ps7
ramb18e1
rambfifo36e1
reg
slicel
slicem
spram32
srlc16e_vpr
srlc16e_vpr_0
srlc16e_vpr_1
srlc32e_vpr
srusedmux
tieoff
wemux
Project Trellis
Index of Primitive Models
BB
CCU2C
DPR16X4C
IB
INV
L6MUX21
LUT2
LUT4
OB
OBZ
PFUMX
TRELLIS_DPR16X4
TRELLIS_FF
TRELLIS_IO
TRELLIS_RAM16X2
Project IceStorm
Index of Primitive Models
dff
dffe
dffes
dffs
dsp
io_local
lutff
pio
pio-b
pio-l
pio-lr
pio-r
pio-t
pio-tb
plb
ram
ramb
ramt
sb_carry
sb_ff
sb_io
sb_lut
sb_pio
sb_ram
Index of Arch Models
tile-routing-virt
top-routing-virt
symbiflow-arch-defs
Table Of Contents
Getting Started
Development Practices
Structure
Verilog To Routing Notes
Project X-Ray
Flow Diagram
VPR routing graph
Xilinx 7 Series SymbiFlow Partial Reconfiguration Flow
Index of Primitive Models
a_srl
alu
b_dram
bram
bram_l
bram_r
bufgctrl
carry0
carry4_vpr
carryinsel_logic
ceusedmux
clkinv
common_lut_and_f78mux
common_slice
coutused
d_dram
d_dram128
di64_stub
dpram32
dpram64
dpram64_for_ram128x1d
dram_2_output_stub
dram_4_output_stub
dram_8_output_stub
dsp48e1
dual_ad_preadder
dual_b_reg
ff
idelayctrl
idelaye2
ilogice3
inpad
iob33
iob33m
iob33s
mult25x18
nmux2
nreg
ologice3
outpad
plle2_adv
ps7
ramb18e1
rambfifo36e1
reg
slicel
slicem
spram32
srlc16e_vpr
srlc16e_vpr_0
srlc16e_vpr_1
srlc32e_vpr
srusedmux
tieoff
wemux
Project Trellis
Index of Primitive Models
BB
CCU2C
DPR16X4C
IB
INV
L6MUX21
LUT2
LUT4
OB
OBZ
PFUMX
TRELLIS_DPR16X4
TRELLIS_FF
TRELLIS_IO
TRELLIS_RAM16X2
Project IceStorm
Index of Primitive Models
dff
dffe
dffes
dffs
dsp
io_local
lutff
pio
pio-b
pio-l
pio-lr
pio-r
pio-t
pio-tb
plb
ram
ramb
ramt
sb_carry
sb_ff
sb_io
sb_lut
sb_pio
sb_ram
Index of Arch Models
tile-routing-virt
top-routing-virt
INV
¶
Component Diagram
¶
`default_nettype none module INV(input A, output Z); assign Z = !A; endmodule
Internal Diagram
¶
Verilog File
¶
`default_nettype
none
module
INV
(
input
A
,
output
Z
);
assign
Z
=
!
A
;
endmodule
Table Of Contents
INV
Component Diagram
Internal Diagram
Verilog File
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