dpram64_for_ram128x1d¶
Physical Block XML¶
<!-- Single port 64x1 DRAM. Used in 128x1 modes.
This pb_type is the same as SPRAM64, except that WA7USED is set.
Because WA7USED is a slice wide, the upper and lower DRAMs must be in
128-bit. This special casing is not required for 256x1 mode because it
always consumes the entire slice, so there is no ambiguity.
-->
<pb_type name="DPRAM64_for_RAM128X1D" num_pb="1" blif_model=".subckt DPRAM64_for_RAM128X1D">
<clock name="CLK" num_pins="1" />
<!-- A1 - Read port -->
<input name="A" num_pins="6" />
<output name="O" num_pins="1" />
<delay_matrix type="max" in_port="A" out_port="O">
{iopath_A1_O6}
{iopath_A1_O6}
{iopath_A1_O6}
{iopath_A1_O6}
{iopath_A1_O6}
{iopath_A1_O6}
</delay_matrix>
<!-- B1 - Write Port -->
<input name="WA" num_pins="6" />
<input name="WA7" num_pins="1" />
<input name="DI" num_pins="1" />
<input name="WE" num_pins="1" />
<T_setup value="{setup_CLK_WA1}" port="WA[0]" clock="CLK" />
<T_setup value="{setup_CLK_WA2}" port="WA[1]" clock="CLK" />
<T_setup value="{setup_CLK_WA3}" port="WA[2]" clock="CLK" />
<T_setup value="{setup_CLK_WA4}" port="WA[3]" clock="CLK" />
<T_setup value="{setup_CLK_WA5}" port="WA[4]" clock="CLK" />
<T_setup value="{setup_CLK_WA6}" port="WA[5]" clock="CLK" />
<T_setup value="{setup_CLK_WA7}" port="WA7" clock="CLK" />
<T_hold value="{hold_CLK_WA1}" port="WA[0]" clock="CLK" />
<T_hold value="{hold_CLK_WA2}" port="WA[1]" clock="CLK" />
<T_hold value="{hold_CLK_WA3}" port="WA[2]" clock="CLK" />
<T_hold value="{hold_CLK_WA4}" port="WA[3]" clock="CLK" />
<T_hold value="{hold_CLK_WA5}" port="WA[4]" clock="CLK" />
<T_hold value="{hold_CLK_WA6}" port="WA[5]" clock="CLK" />
<T_hold value="{hold_CLK_WA6}" port="WA7" clock="CLK" />
<T_clock_to_Q max="{iopath_CLK_O6}" port="WA" clock="CLK" />
<T_clock_to_Q max="{iopath_CLK_O6}" port="WA7" clock="CLK" />
<T_setup value="{setup_CLK_WE}" port="WE" clock="CLK" />
<T_hold value="{hold_CLK_WE}" port="WE" clock="CLK" />
<T_clock_to_Q max="{iopath_CLK_O6}" port="WE" clock="CLK" />
<T_setup value="{setup_CLK_DI1}" port="DI" clock="CLK" />
<T_hold value="{hold_CLK_DI1}" port="DI" clock="CLK" />
<T_clock_to_Q max="{iopath_CLK_O6}" port="DI" clock="CLK" />
<metadata>
<meta name="fasm_params">
INIT[63:0] = INIT
</meta>
<meta name="fasm_features">
RAM
</meta>
<meta name="type">bel</meta>
<meta name="subtype">memory</meta>
</metadata>
</pb_type>