idelaye2¶

Physical Block XML¶

<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="IDELAYE2" blif_model=".subckt IDELAYE2_VPR" num_pb="1">
  <clock name="C" num_pins="1"/>
  <input name="CE" num_pins="1"/>
  <input name="CINVCTRL" num_pins="1"/>
  <input name="CNTVALUEIN0" num_pins="1"/>
  <input name="CNTVALUEIN1" num_pins="1"/>
  <input name="CNTVALUEIN2" num_pins="1"/>
  <input name="CNTVALUEIN3" num_pins="1"/>
  <input name="CNTVALUEIN4" num_pins="1"/>
  <input name="DATAIN" num_pins="1"/>
  <input name="IDATAIN" num_pins="1"/>
  <input name="INC" num_pins="1"/>
  <input name="LD" num_pins="1"/>
  <input name="LDPIPEEN" num_pins="1"/>
  <input name="REGRST" num_pins="1"/>
  <output name="CNTVALUEOUT0" num_pins="1"/>
  <output name="CNTVALUEOUT1" num_pins="1"/>
  <output name="CNTVALUEOUT2" num_pins="1"/>
  <output name="CNTVALUEOUT3" num_pins="1"/>
  <output name="CNTVALUEOUT4" num_pins="1"/>
  <output name="DATAOUT" num_pins="1"/>

  <!-- fake timing values -->
  <T_setup value="10e-12" port="CE" clock="C" />
  <T_hold value="10e-12" port="CE" clock="C" />
  <T_setup value="10e-12" port="INC" clock="C" />
  <T_hold value="10e-12" port="INC" clock="C" />
  <T_setup value="10e-12" port="LD" clock="C" />
  <T_hold value="10e-12" port="LD" clock="C" />
  <T_setup value="10e-12" port="REGRST" clock="C" />
  <T_hold value="10e-12" port="REGRST" clock="C" />

  <!-- TODO
       - correct timing values
  -->
  <metadata>
    <meta name="fasm_params">
      IN_USE = IN_USE
      IDELAY_VALUE[4:0] = IDELAY_VALUE

      ZIDELAY_VALUE[4:0] = ZIDELAY_VALUE

      IS_DATAIN_INVERTED = IS_DATAIN_INVERTED
      IS_IDATAIN_INVERTED = IS_IDATAIN_INVERTED

      PIPE_SEL = PIPE_SEL
      CINVCTRL_SEL = CINVCTRL_SEL

      HIGH_PERFORMANCE_MODE = HIGH_PERFORMANCE_MODE

      IDELAY_TYPE_FIXED = IDELAY_TYPE_FIXED
      IDELAY_TYPE_VAR_LOAD = IDELAY_TYPE_VAR_LOAD
      IDELAY_TYPE_VARIABLE = IDELAY_TYPE_VARIABLE

      DELAY_SRC_DATAIN = DELAY_SRC_DATAIN
      DELAY_SRC_IDATAIN = DELAY_SRC_IDATAIN
    </meta>
  </metadata>
</pb_type>

Model XML¶

<models>
  <model name="IDELAYE2_VPR">
    <input_ports>
      <!-- synchronous control inputs -->
      <port is_clock="1" name="C"/>
      <port clock="C" name="CE"/>
      <port clock="C" name="INC"/>
      <port clock="C" name="LD"/>
      <port clock="C" name="REGRST"/>

      <port name="CINVCTRL"/>
      <port name="CNTVALUEIN0"/>
      <port name="CNTVALUEIN1"/>
      <port name="CNTVALUEIN2"/>
      <port name="CNTVALUEIN3"/>
      <port name="CNTVALUEIN4"/>
      <port name="DATAIN"/>
      <port name="IDATAIN"/>
      <port name="LDPIPEEN"/>
    </input_ports>
    <output_ports>
      <port name="CNTVALUEOUT0"/>
      <port name="CNTVALUEOUT1"/>
      <port name="CNTVALUEOUT2"/>
      <port name="CNTVALUEOUT3"/>
      <port name="CNTVALUEOUT4"/>
      <port name="DATAOUT"/>
    </output_ports>
  </model>
</models>