coutused¶
Component Diagram¶
Internal Diagram¶
Verilog File¶
`include "../../../../../../vpr/muxes/logic/mux2/mux2.sim.v"
module COUTUSED(IN, OUT);
input wire IN;
parameter S = 0;
output wire OUT;
MUX2 mux (
.I0(0),
.I1(IN),
.S0(S),
.O(OUT)
);
endmodule
Physical Block XML¶
<pb_type name="COUTUSED" num_pb="1">
<input name="IN" num_pins="1"/>
<output name="OUT" num_pins="1"/>
<interconnect>
<mux input="COUTUSED.IN" name="_COUTUSED" output="COUTUSED.OUT"/>
</interconnect>
</pb_type>