b_dram¶
Physical Block XML¶
<pb_type name="B_DRAM" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">
<clock name="CLK" num_pins="1" />
<input name="A" num_pins="6" />
<input name="WA" num_pins="8" />
<input name="DI1" num_pins="1" />
<input name="DI2" num_pins="1" />
<input name="WE" num_pins="1" />
<output name="DO6" num_pins="1" />
<output name="DO6_32" num_pins="1" />
<output name="DO5_32" num_pins="1" />
<output name="O6" num_pins="1" />
<output name="O5" num_pins="1" />
<output name="DO1" num_pins="1" />
<!-- TODO: Missing modes: SRL -->
<mode name="LUT">
<xi:include href="../../common_slice/Nlut/blut.pb_type.xml" />
<interconnect>
<direct name="A1" input="B_DRAM.A[0]" output="BLUT.A1"/>
<direct name="A2" input="B_DRAM.A[1]" output="BLUT.A2"/>
<direct name="A3" input="B_DRAM.A[2]" output="BLUT.A3"/>
<direct name="A4" input="B_DRAM.A[3]" output="BLUT.A4"/>
<direct name="A5" input="B_DRAM.A[4]" output="BLUT.A5"/>
<direct name="A6" input="B_DRAM.A[5]" output="BLUT.A6"/>
<direct name="O5" input="BLUT.O5" output="B_DRAM.O5"/>
<direct name="O6" input="BLUT.O6" output="B_DRAM.O6"/>
</interconnect>
</mode>
<mode name="64_DUAL_PORT">
<xi:include href="dpram64.pb_type.xml" />
<interconnect>
<direct name="CLK" input="B_DRAM.CLK" output="DPRAM64.CLK" />
<direct name="A" input="B_DRAM.A" output="DPRAM64.A" />
<direct name="WA" input="B_DRAM.WA[5:0]" output="DPRAM64.WA[5:0]" />
<direct name="WA7" input="B_DRAM.WA[6]" output="DPRAM64.WA7" />
<direct name="WA8" input="B_DRAM.WA[7]" output="DPRAM64.WA8" />
<direct name="DI" input="B_DRAM.DI1" output="DPRAM64.DI" />
<direct name="WE" input="B_DRAM.WE" output="DPRAM64.WE" />
<direct name="O6" input="DPRAM64.O" output="B_DRAM.O6" />
<direct name="DO6" input="DPRAM64.O" output="B_DRAM.DO6" />
<direct name="DIPAS" input="B_DRAM.DI1" output="B_DRAM.DO1" />
</interconnect>
<metadata>
<meta name="fasm_prefix">BLUT</meta>
</metadata>
</mode>
<mode name="32_DUAL_PORT">
<pb_type name="DPRAM32_O6" num_pb="1" blif_model=".subckt DPRAM32">
<xi:include href="dpram32.pb_type.xml" xpointer="xpointer(pb_type/child::node()[local-name()!='metadata'])" />
<metadata>
<xi:include href="dpram32.pb_type.xml" xpointer="xpointer(pb_type/metadata/child::node())" />
<meta name="fasm_params">
INIT[63:32] = INIT_00
</meta>
</metadata>
</pb_type>
<pb_type name="DPRAM32_O5" num_pb="1" blif_model=".subckt DPRAM32">
<xi:include href="dpram32.pb_type.xml" xpointer="xpointer(pb_type/child::node()[local-name()!='metadata'])" />
<metadata>
<xi:include href="dpram32.pb_type.xml" xpointer="xpointer(pb_type/metadata/child::node())" />
<meta name="fasm_params">
INIT[31:0] = INIT_00
</meta>
</metadata>
</pb_type>
<interconnect>
<!-- upper -->
<direct name="CLK_U" input="B_DRAM.CLK" output="DPRAM32_O6.CLK" />
<direct name="A_U" input="B_DRAM.A[4:0]" output="DPRAM32_O6.A[4:0]" />
<direct name="WA_U" input="B_DRAM.WA[4:0]" output="DPRAM32_O6.WA[4:0]" />
<direct name="DI2" input="B_DRAM.DI2" output="DPRAM32_O6.DI" />
<direct name="WE_U" input="B_DRAM.WE" output="DPRAM32_O6.WE" />
<direct name="O6" input="DPRAM32_O6.O" output="B_DRAM.O6" />
<direct name="DO6" input="DPRAM32_O6.O" output="B_DRAM.DO6_32" >
<pack_pattern out_port="B_DRAM.DO6_32" name="DRAM_8O_32" in_port="DPRAM32_O6.O" />
<pack_pattern out_port="B_DRAM.DO6_32" name="DRAM_DP_32_HI" in_port="DPRAM32_O6.O" />
<pack_pattern out_port="B_DRAM.DO6_32" name="DRAM_DP_32_LO" in_port="DPRAM32_O6.O" />
</direct>
<!-- lower -->
<direct name="CLK_L" input="B_DRAM.CLK" output="DPRAM32_O5.CLK" />
<direct name="A_L" input="B_DRAM.A[4:0]" output="DPRAM32_O5.A[4:0]" />
<direct name="WA_L" input="B_DRAM.WA[4:0]" output="DPRAM32_O5.WA[4:0]" />
<direct name="DI" input="B_DRAM.DI1" output="DPRAM32_O5.DI" />
<direct name="WE_L" input="B_DRAM.WE" output="DPRAM32_O5.WE" />
<direct name="O5" input="DPRAM32_O5.O" output="B_DRAM.O5" />
<direct name="DO5" input="DPRAM32_O5.O" output="B_DRAM.DO5_32" >
<pack_pattern out_port="B_DRAM.DO5_32" name="DRAM_8O_32" in_port="DPRAM32_O5.O" />
<pack_pattern out_port="B_DRAM.DO5_32" name="DRAM_DP_32_HI" in_port="DPRAM32_O5.O" />
<pack_pattern out_port="B_DRAM.DO5_32" name="DRAM_DP_32_LO" in_port="DPRAM32_O5.O" />
</direct>
</interconnect>
<metadata>
<meta name="fasm_prefix">BLUT</meta>
</metadata>
</mode>
<mode name="32_SINGLE_PORT">
<pb_type name="SPRAM32_O6" num_pb="1" blif_model=".subckt SPRAM32">
<xi:include href="spram32.pb_type.xml" xpointer="xpointer(pb_type/child::node()[local-name()!='metadata'])" />
<metadata>
<xi:include href="spram32.pb_type.xml" xpointer="xpointer(pb_type/metadata/child::node())" />
<meta name="fasm_params">
INIT[63:32] = INIT_00
INIT[31:0] = INIT_ZERO
</meta>
</metadata>
</pb_type>
<interconnect>
<direct name="CLK_U" input="B_DRAM.CLK" output="SPRAM32_O6.CLK" />
<direct name="A_U" input="B_DRAM.A[4:0]" output="SPRAM32_O6.A[4:0]" />
<direct name="WA_U" input="B_DRAM.WA[4:0]" output="SPRAM32_O6.WA[4:0]" />
<direct name="DI2" input="B_DRAM.DI2" output="SPRAM32_O6.DI" />
<direct name="WE_U" input="B_DRAM.WE" output="SPRAM32_O6.WE" />
<direct name="O6" input="SPRAM32_O6.O" output="B_DRAM.O6" />
<direct name="DO6" input="SPRAM32_O6.O" output="B_DRAM.DO6_32" >
<pack_pattern out_port="B_DRAM.DO6_32" name="DRAM_QP_32" in_port="SPRAM32_O6.O"/>
</direct>
</interconnect>
<metadata>
<meta name="fasm_prefix">BLUT</meta>
</metadata>
</mode>
<metadata>
<meta name="type">block</meta>
<meta name="subtype">ignore</meta>
</metadata>
</pb_type>