dram_2_output_stub
===============================================================================



Component Diagram
-----------------

.. symbolator:: ../../../../../xc/common/primitives/slicem/dram_2_output_stub.sim.v

   

Internal Diagram
----------------

.. verilog-diagram:: ../../../../../xc/common/primitives/slicem/dram_2_output_stub.sim.v
   :type: netlistsvg
   :module: DRAM_2_OUTPUT_STUB

   

Verilog File
------------

.. literalinclude:: ../../../../../xc/common/primitives/slicem/dram_2_output_stub.sim.v
   :language: verilog