TRELLIS_RAM16X2
===============================================================================



Component Diagram
-----------------

.. symbolator:: ../../../../../ecp5/primitives/slice/TRELLIS_RAM16X2/TRELLIS_RAM16X2.sim.v

   

Internal Diagram
----------------

.. verilog-diagram:: ../../../../../ecp5/primitives/slice/TRELLIS_RAM16X2/TRELLIS_RAM16X2.sim.v
   :type: netlistsvg
   :module: TRELLIS_RAM16X2

   

Verilog File
------------

.. literalinclude:: ../../../../../ecp5/primitives/slice/TRELLIS_RAM16X2/TRELLIS_RAM16X2.sim.v
   :language: verilog